Internal Register Set

CHX0023

North Module

Bus 0 Device 0 Function 2

SVAD DVAD Control

Revision 00252

July 10, 2019March 7, 2019

Shanghai Zhaoxin Semiconductor

IRS Revision History

Doc Rev.	Chip Rev.	Date	Revision Descriptions	Department	Name
R052	A0	7/9/2019	Change Rx90[31:28] HW attr to RO Change RxB8[31:3] SW attr to RO and HW attr to NA Correct default value for RSVAD_MEXXLADDR[45:28] and RTopA Correct some description	NB	Chunhui Zheng
R051	A0	6/25/2019	Update SVAD according to SW review result	CPU	Sharon Gao
R050	A0	6/14/2019	Update PCI Config space Figure	NB	Chunhui Zheng
R003	A0	3/15/2019	add RSVAD_MMIOB2G_DIS at Rx9C[1]	NB	Chunhui Zheng
R002	A0	43/148/20179	add PCIE capability and Power Management Capability move SVAD register to Rx90h~Rx3FFh, TPR start offset to Rx400h Remove DVAD registers Add legacy IO decoder by Sharon Add DPR control	NB	Chunhui Zheng
R001	A0	3/6/2019	Initial internal release based on CHX002	CPU	Sharon Gao

Lists of TIC Tags

TIC Question Tag

([TIC Question 1. End of questions. Thanks!])63

TIC Editing Tag

([ TIC Editing Note 1. The default value should be changed to nnnnh in SPM. ])12

IRS Revision History1

Lists of TIC Tags2

TIC Question Tag2

TIC Editing Tag2

Table of Contents3

List of Tables4

List of Figures4

IRS Style Brief Introduction (For IRS Rule V3.R3)5

Tags and Colors5

Columns of The Register Table5

Columns of Suggested Values:5

IRS Register Attributes7

Attribute Definitions7

Default Value Definitions8

Device 0 Function 2 (D0F2): System SVAD DVAD Controller9

PCI Configuration Space9

Header Registers (00-3Fh)12

System View Address Decode (40-BFh)19

TPR Control (C0-CFh)51

DRAM View Address Decode (D0-EFh)54

List of Tables

Table 1. SVAD Decode for SMM47

List of Figures

Figure 1. System Block Diagram for D0F29

Figure 2. Register Level Block Diagram for D0F29

IRS Style Brief Introduction (For IRS Rule V3.R3)

Tags and Colors

To distinguish different levels of confidentiality, TIC uses “tags” and “colors” to identify registers with different purposes. Each of them represents different meanings.

Tags and Colors Used by TIC

TIC Question Tag: This tag is used for questions and issues. All questions in IRS will also be listed in the TOC section.
TIC Editing Note : Notes for TIC writers as editing reminders.
TIC XXX Feature Tag: To point out the related registers with some specific product features.
All TIC tags are enclosed between square brackets that are set inside parenthesis. “([…])”
Color Used For Internal Content
((Internal Content)): Used to represent internal registers or contents that cannot be released to customers.

Double parenthesis “(( ... ))“ will be added before and after the internal registers or contents.
“For Internal Reference[..]” should be added before those contents or after register names.
Internal signal names can NOT be used in external content. (Only top module names are allowed to be public)

How to use Highlight:

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Columns of The Register Table

Default: Default value of this register. Only allow using binary/hexadecimal value (or 0) in this field.
The defined keywords for special default values are listed as follows.

Dip : the default value is set by dip switch or strapping.
HwInit: Hardware initialized; bit default value is set by hardware to reflect related status.
ROMSIP: The default value is defined in ROMSIP.
((Bonding)): The default value is depend on different product.

Mnemonic: An asterisk (*) before a mnemonic indicates this mnemonic is referenced in some other content.
PwrDm: Power Domain. Following values can be used to indicate the power source of this register:

vbat : for battery well
vsus : for suspend well
vcc: for VCC well

Others: Please refer to Outlook:\\RD_Project\# IRS Guideline\Checker&Rules\IRS Checker-Format Rules.doc
for more details.
Columns of Suggested Values:
S: Stable/Safe. Set to this value for best stability and/or reliability.
At least make sure the system can be booted without any problem.
Stability = the system can be run over periods of time without crashing or otherwise malfunctioning.
Reliability = perform the required functions under stated conditions for a specified period of time.
P: Performance. Set to this value for taking less time to complete the required task.
E: Energy. Set to this value for power saving.

The Suggestion Values:

0/1 : ( without the suffix ‘b’ ) Indicates the binary value for the setting. (ex. 010)
h : Use suffix ‘h’ to indicate the hex value. (ex.6Ah)
R : Indicates the RO register with fixed register value. No suggestion value will be provided.
x : Indicates the value is don't-care. No suggestion value will be provided. (ex. x)
* : Indicates the setting depends on other bits or requires specific programming sequence.
The detailed setting information should be described in bit description column. (ex. *10)

IRS Register Attributes

Attribute Definitions

Basic Attributes: indicate common read-write operations.

RO:Read Only.

WO:Write Only. (register value can not be read by the software)

RW:Read / Write.

RW1:Write Once then Read Only after that.

RW1C:Read / Write of “1” clears bit to zero.

RWL:Lockable Read / Write. Read/writable with lock bit control: RW when lock bit=0, Read-Only when lock bit=1.

Extended Attributes: indicate combinational or internal access methods.

RO((shadow)): Value of this register is copied from another register.

RO((RW)):Used to indicate the existence of the internal guard bit.

RO/RW:Used to indicate the public guard bit. (ex. if the guard bit is defined in spec)

RW((RWHC)): R/W-able with hardware clear automatically.

Sticky Attributes:

Adding an “S” in tail indicates a sticky register, which means that register will not be set or altered by hot reset.

Adding the “RS” in tail indicates a reset-sticky register, which means that register will not be reset unless the system entered S4/S5 state.

ROS: Sticky-Read-Only.

WOS: Sticky-Write-Only.

RWS: Sticky-Read/Write.

RW1S:Sticky-Write-Once.

RW1CS:Sticky-Write-1-to-Clear.

RWLS:Sticky-Lockable Read/Write.

RORS: Reset-Sticky-Read-Only.

WORS:Reset-Sticky-Write-Only.

RWRS: Reset-Sticky-Read/Write.

RW1RS:Reset-Sticky-Write-Once.

RW1CRS: Reset-Sticky-Write-1-to-Clear.

ROS((shadows)):Sticky-shadow

ROS((RWS)):Sticky-RO((RW))

ROS/RWS:Sticky-RO/RW

RW((RWHC))S: Sticky-RW((RWHC))

RORS((shadows)):Reset-Sticky-shadow

RORS((RWS)):Reset-Sticky-RO((RW))

RORS/RWRS:Reset-Sticky-RO/RW

RW((RWHC))RS:Reset-Sticky-RW((RWHC))

((Internal Notes:

1. For RW1Set in xHCI spec: per discussion, it is the same with RW((RWHC)).

RW1Set: Read / Write of “1” sets bit to “1”. (Writing a 0 has no effect)

RW1SetS: Sticky-Write-1-to-Set ))

Default Value Definitions

Dip:Means the default value is set by dip switch or strapping.

HwInit:Hardware initialized; bit default value is set by hardware to reflect related status.

ROMSIP: The default will be overwritten by the value defined in ROMSIP after system reset.

(( Bonding: The default value depends on different product. ))

Device 0 Function 2 (D0F2): System SVAD DVAD Controller

@((SOURCE: CHIP_SRC=CHX0022(A0), DOC_SRC= CHX0023 IRS_NB_D0F2_SVADDVAD_R0013, IRS_STYLE_VER=V3 ))

@((MODULE(MOD_D0F2, 1x1): PRJ=CHX0023, REG_SPACE_NUM=1, ADDR_WIDTH=12 ))

@((REG_SPACE [0]: TYPE=PCI, NAME=D0F2, SEL=AD11, SPACE_LEVEL=1, RANGE=(0h, FFFh) ))

@((DEFAULT_GUARDBIT=RPEROWEN D0F5 RXF0[0]))

@((REG_GROUP(PCI Header Registers): RANGE=(0h, 3Fh) ))

PCI Configuration Space

This chip integrates the functions of conventional chipset North Bridge, South Bridge and the Graphics Controller (GFXCTL) into one single chip. The traditional functions of North Bridge is included in the North Module (NM) of this chip; while the functions of traditional South Bridge, like PCI bus controller and ISA controller, are included in the South Module (SM) of this chip, as shown in Figure 1 below.

Device 0 Function 2 is a Host Bridge. All registers in this function are located in PCI configuration space and should be programmed using PCI configuration mechanism 1 through I/O registers CF8 / CFC with bus number 0, device number 0 and function number 2. For example, I/O write CF8h, with the data having the following format. And then I/O read CFCh, to get the data or I/O write CFCh, to write data (32 bits). Registers in this function can also be accessed using PCIE enhanced configuration mechanism when it is enabled by programming D0F2Rx40[17:0].

Bit [31]	Bits [30:24]	Bits [23:16]	Bits [15:11]	Bits [10:8]	Bits [7:2]	Bit [1]	Bit [0]
Enable	Reserved	Bus Number	Device Number	Function Number	Register Number	0	0
1	000_0000	0000_0000	0_0000	010	RX offset address with bit [1:0] = 00b

Figure 1. System Block Diagram for D0F2

Figure 2. Register Level Block Diagram for D0F2

Header Registers (00-3Fh)

Rx00-Rx3F are PCI header registers. Please refer to PCI specification for more information.

([ TIC Editing Note 1. The default value should be changed to nnnnh in SPM. ])

Offset Address: 01-00h (D0F2)
Vendor IDDefault Value: 1D17h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RO((RWL))	NA	1D17h	Vendor ID Used to identify the manufacturer of this device. ((For Internal Reference: @((#USER=PCISPEC)) @((#control_lock=lock_port D0F2_RX40B29RVID_DID_LOCK_D0F2)) @((#control_default=NB_VID_SEL)) @((#VENDOR_OPTION=1106h)) ))	VendorID[15:0]		vcc	x	x	x

Offset Address: 03-02h (D0F2)
Device IDDefault Value: 31B1h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RO((RWL))	NA	31B1h	Device ID Used to identify this function. ((For Internal Reference: @((#USER=PCISPEC)) @((#control_lock=lock_port D0F2_RX40B31RDID_RID_LOCK_D0F2)) ))	DEVID[15:0]		vcc	x	x	x

Offset Address: 05-04h (D0F2)
PCI CommandDefault Value: 0006h

The bit values of this register are fixed and they do not affect any behavior on the PCI bus. ((For Internal Reference: The behavior of the PCI bus is controlled by the PCI command registers on D17F7 (when D17F7Rx4F[6](RENPPB) = 0) or D19F0 (when D17F7Rx4F[6](RENPPB) = 1).))

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:10	RO	NA	0	Reserved	Rx04[15:10]		vcc	R	x	x
9	RO	NA	0	Fast Back-to-back Cycle Enable It is used to enable the fast back-to-back capability on the PCI bus for the PCI bus controller.	RFBACK		vcc	R	x	x
8	RO	NA	0	SERR# Enable It is used to enable the SERR# driver which asserts SERR# signal on the PCI bus.	RSERR		vcc	R	x	x
7	RO	NA	0	Address/Data Stepping It is used to enable the address/data stepping for PCI bus controller to generate cycles on the PCI bus.	RSETP		vcc	R	x	x
6	RO	NA	0	Parity Error Response It is used to tell the PCI bus controller to perform the parity check on the PCI bus or not.	*RPTYERR		vcc	R	x	x
5	RO	NA	0	VGA Palette Snooping It controls how VGA compatible Graphics devices handle accesses to VGA palette registers. This bit is fixed at 0.	RVGA		vcc	R	x	x
4	RO	NA	0	Memory Write and Invalidate It is used to enable the PCI bus controller to issue Memory Write Invalidate command on the PCI bus.	RMWINV		vcc	R	x	x
3	RO	NA	0	Respond to Special Cycle It is used to enable the PCI bus controller to take actions once it sees a special cycle on the PCI bus.	RSPCYC		vcc	R	x	x
2	RO	NA	1b	PCI Master Function It is used to enable the PCI bus controller to issue cycles to devices on the PCI bus.	RMSTR		vcc	R	x	x
1	RO	NA	1b	Memory Space Access It is used to enable the PCI bus controller to accept the memory cycles from devices on the PCI bus.	RENMEM		vcc	R	x	x
0	RO	NA	0	I/O Space Access It is used to enable the PCI bus controller to accept the I/O cycles from devices on the PCI bus.	RENIO		vcc	R	x	x

Offset Address: 07-06h (D0F2)
PCI StatusDefault Value: 02010h

The value of this register won’t reflect what happened on the PCI bus. ((For Internal Reference: The status of the PCI bus is reported to the PCI Status Register at D17F7 (when D17F7 Rx4F[6](RENPPB) = 0) or D19F0 (when D17F7 Rx4F[6](RENPPB) = 1).))

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15	RO	NA	0	Detected Parity Error It is used to indicate a parity error had been detected by the PCI bus controller.	SPERRS		vcc	R	x	x
14	RO	NA	0	Signaled System Error (SERR# Asserted) It is used to indicate the PCI bus controller had asserted the SERR#.	SERRS		vcc	R	x	x
13	RO	NA	0	Received Master-abort (Except Special Cycle) It is used to indicate the PCI bus controller encountered a cycle termination by master abort for its transaction.	SMABORT		vcc	R	x	x
12	RO	NA	0	Received Target-abort It is used to indicate the PCI bus controller encountered a cycle termination by target abort for its transaction.	STABORTM		vcc	R	x	x
11	RO	NA	0	Target-abort Assertion It is used to indicate the PCI bus controller issued a target abort termination for the cycle targeted to it.	STABORTS		vcc	R	x	x
10:9	RO	NA	01b	DEVSEL# Timing It is used to indicate the response latency for the timing of PCI signal DEVSEL#. 00: Fast01: Medium 10: Slow11: Reserved These bits won’t affect the DEVSEL# timing on the PCI bus.	DEVS[1:0]		vcc	R	x	x
8	RO	NA	0	Master Data Parity Error It is used to tell that PERR# on the PCI bus is asserted to indicate a possible parity error happened. It includes three cases: As a target, the PCI bus controller asserts PERR# on a read cycle or observes the assertion of PERR# on a write cycle. As a initiator, the PCI bus controller encounters error upon the cycle it initiates. Parity Error Response bit at Rx04[6](RPTYERR) is set.	SDPERRS		vcc	R	x	x
7	RO	NA	0	Capable of Accepting Fast Back-to-back as a Target It is used to indicate the capability of accepting fast back-to-back cycles.	RFBKS		vcc	R	x	x
6	RO	NA	0	User Definable Features It is reserved for user to define.	RUDF		vcc	R	x	x
5	RO	NA	0	66MHz Capability It is used to indicate the capability of supporting 66Mhz for the PCI bus controller. ((For Internal Reference: @((EXT = ECO)) ))	R66M		vcc	R	x	x
4	RO	NA	1b0	Support New Capability List It indicates whether this device implements the pointer for a New Capabilities linked list at offset 34h. 0: New capability linked list is not available. 1: The value read at offset 34h is a pointer in configuration space to a linked list of new capabilities, i.e., new capability linked list is supported.	RCAP		vcc	R	x	x
3:0	RO	NA	0	Reserved	Rx04[19:16]		vcc	R	x	x

Offset Address: 08h (D0F2)
Revision IDDefault Value: 04h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO((RWL))	NA	04h	Revision Code It indicates the revision ID of this function. ((For Internal Reference: @((#USER=PCISPEC)) @((#control_lock=lock_port D0F2_RX40B31RDID_RID_LOCK_D0F2)) ))	Rx08[7:0]		vcc	x	x	x

Offset Address: 0B-09h (D0F2)
Class CodeDefault Value: 06 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
23:0	RO((RWL))	NA	06 0000h	Class Code 06 0000h indicates this function is a host bridge. ((For Internal Reference: @((#USER=PCISPEC)) @((#control_lock=lock_port D0F2_RX40B27RCLASS_CODE_LOCK_D0F2)) ))	ClassCode[23:0]		vcc	x	x	x

Offset Address: 0Ch (D0F2)
Cache Line SizeDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RW	NA	0	Cache Line Size It indicates the cache-line size in a cache-line transaction in units of double words. ((Writing 1 or 0 to these registers does not change any behavior of this chip.)) ((For Internal Reference: Some HCT software requires these registers to be R/W to have warning free report.))	Rx0C[7:0]		vcc	x	x	x

Offset Address: 0Dh (D0F2)
PCI Master Latency TimerDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Maximum Time Slice for This Function as a Master on the PCI Bus It indicates how many PCI clocks of duration the PCI controller as a master can own the PCI bus. The unit is 8 PCI Clocks. They do not have any impact to the behaviors of this chip.	Rx0C[15:8]		vcc	R	x	x

Offset Address: 0Eh (D0F2)
Header TypeDefault Value: 80h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	80h	Header Type Bit [7] in this register is used to identify a multifunction device. If bit [7] = 0, the device is single function. If bit [7] = 1, the device is multiple functions. Bits [6:0] identify the layout of the second part of the predefined header. 00h is the header type for this host bridge. The value 80h indicates that this is a multi-function device.	Rx0C[23:16]		vcc	R	x	x

Offset Address: 0Fh (D0F2)
Built In Self Test (BIST)Default Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	BIST Support Bit [7] = 0 indicates that this function does not support BIST. Writing a 1 to bit [6] will invoke the BIST operation. The value of 0h on bits [3:0] means the device has passed its test. Non-zero values on bits [3:0] means the device failed. This chip does not support BIST through these registers.	Rx0C[31:24]		vcc	R	x	x

Offset Address: 13-10h (D0F2)
Base Address Registers 0Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RO	NA	0	Base Address 0 This function does not claim base address.	Rx10[31:0]		vcc	R	x	x

Offset Address: 17-14h (D0F2)
Base Address Registers 1Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RO	NA	0	Base Address 1 This function does not claim base address.	Rx14[31:0]		vcc	R	x	x

Offset Address: 1B-18h (D0F2)
Base Address Registers 2Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RO	NA	0	Base Address 2 This function does not claim base address.	Rx18[31:0]		vcc	R	x	x

Offset Address: 1F-1Ch (D0F2)
Base Address Registers 3Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RO	NA	0	Base Address 3 This function does not claim base address.	Rx1C[31:0]		vcc	R	x	x

Offset Address: 23-20h (D0F2)
Base Address Registers 4Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RO	NA	0	Base Address 4 This function does not claim base address.	Rx20[31:0]		vcc	R	x	x

Offset Address: 27-24h (D0F2)
Base Address Registers 5Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RO	NA	0	Base Address 5 This function does not claim base address.	Rx24[31:0]		vcc	R	x	x

Offset Address: 2B-28h (D0F2)
CardBus CIS PointerDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RO	NA	0	CardBus CIS Pointer This field is used to point to the Card Information Structure (CIS) for the CardBus Card. It is not supported by this function.	Rx28[31:0]		vcc	R	x	x

Offset Address: 2D-2Ch (D0F2)
Subsystem Vendor IDDefault Value: 0001D170h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RW1	NA	01D17h	Subsystem Vendor ID They are used to uniquely identify the manufacturer of the expansion board or subsystem where the PCI device resides. These write once registers can be written once and only once after the de-assertion of PCIRST#.	Rx2C[15:0]		vcc	x	x	x

Offset Address: 2F-2Eh (D0F2)
Subsystem IDDefault Value: 000031B1h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RW1	NA	031B1h	Subsystem ID They are used to uniquely identify the expansion board or subsystem where the PCI device resides. These write once registers can be written once and only once after the de-assertion of PCIRST#.	Rx2C[31:16]		vcc	x	x	x

Offset Address: 30h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx30[7:0]		vcc	R	x	x

Offset Address: 31h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx31[7:0]		vcc	R	x	x

Offset Address: 32h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx32[7:0]		vcc	R	x	x

Offset Address: 33h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx33[7:0]		vcc	R	x	x

Offset Address: 34h (D0F2)
Capability PointerDefault Value: 40h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO((RW))	NA	40h	Capability List Pointer It indicates an offset address from the start of the configuration space. This pointer points to a linked list of new capabilities implemented by this device. A 0 indicates the end of the list. This function of this chip does not have any capability needed to be specified.	CAPPTR[7:0]		vcc	40h	x	x

Offset Address: 35h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx35[7:0]		vcc	R	x	x

Offset Address: 36h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx36[7:0]		vcc	R	x	x

Offset Address: 37h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx37[7:0]		vcc	R	x	x

Offset Address: 38h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx38[7:0]		vcc	R	x	x

Offset Address: 39h (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx39[7:0]		vcc	R	x	x

Offset Address: 3Ah (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx3A[7:0]		vcc	R	x	x

Offset Address: 3Bh (D0F2)
ReservedDefault Value: 00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
7:0	RO	NA	0	Reserved	Rx3B[7:0]		vcc	R	x	x

Offset Address: 3D-3Ch (D0F2)
Interrupt Line and Interrupt PinDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:8	RO	NA	0	Interrupt Pin It tells which interrupt pin the device uses. It is not applicable to this function.	Rx3C[15:8]		vcc	R	x	x
7:0	RO	NA	0	Interrupt Line It is used to communicate interrupt line routing information. It is not applicable to this function.	Rx3C[7:0]		vcc	R	x	x

Offset Address: 3F-3Eh (D0F2)
Minimum Grant and Maximum LatencyDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:8	RO	NA	0	Maximum Latency It is used to specify how often the device needs to gain access to the PCI bus in units of 1/4 microsecond. It is not applicable to this function.	Rx3C[31:24]		vcc	R	x	x
7:0	RO	NA	0	Minimum Grant It is used to specify how long a burst period this device needs in units of 1/4 microsecond. It is not applicable to this function.	Rx3C[23:16]		vcc	R	x	x

@((REG_GROUP(Multi-Function Control and Legacy Space Access Control): RANGE=(40h, 7Fh) ))

Reserved for PCI Express Capibility (40-7Fh)

Offset Address: 41-40h (D0F0(D0F2)
PCI Express ListDefault Value: 8010h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:8	RO((RW))	NA	80h	Next Pointer This 8-bit pointer points to the next capability of this function. Next capability is resided started from Rx88h	RX40[15:8]		vcc	80h	x	x
7:0	RO	NA	10h	Capability ID This byte is read as 10h indicates a PCI Express Capability Structure.	RX40[7:0]		vcc	10h	x	x

Offset Address: 43-42h (D0F0(D0F2)
PCI Express CapabilitiesDefault Value: 0042h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:14	RO	NA	0	Reserved	RX42[15:14]		vcc	0	x	x
13:9	RO((RW))	NA	0	Interrupt Message Number	RX42[13:9]		vcc	0	x	x
8	RO((RW))	NA	0	Slot Implemented	RX42[8]		vcc	0b	x	x
7:4	RO((RW))	NA	0100b	Device / Port Type	RX42[7:4]		vcc	0100b	x	x
3:0	RO((RW))	NA	2h	Capability Version Bit	RX42[3:0]		vcc	2h	x	x

Offset Address: 47-44h (D0F0(D0F2)
Device Capabilities 1Default Value: 0000 8000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:29	RO	NA	0	Reserved	rsv_19		vcc	R	x	x
28	RO ((RW))	NA	0	Function Level Reset Capability A value of 1 indicates this function supports the optional Function Level Reset (FLR) mechanism. This field applies to Endpoints only. It is reserved for this root port. ((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))	tbd_27		vcc	0	x	x
27:26	RO	NA	0	Captured Slot Power Limit Scale This field specifies the scale used for the Slot Power Limit Value (Rx44[25:18]). Range of values: 00: 1.0x.01: 0.1x. 10: 0.01x.11: 0.001x. Upon receiving the Set_Slot_Power_Limit Message from the upper link, this field is set as the value specified in the message or is hardwired to 00b. This bit is for upstream port only, it is reserved and always read as 00b for this root port.	rsv_20		vcc	0	x	x
25:18	RO	NA	0	Captured Slot Power Limit Value In combination with the Slot Power Limit Scale value (Rx44[27:26]), this field specifies the upper limit on power supplied by slot. Power limit (in Watts) calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field (Rx44[27:26]). Upon receiving the Set_Slot_Power_Limit Message from the upper link, this field is set as the value specified in the message or is hardwired to 00h. This bit is for upstream port only, it is reserved and always read as 00h for this root port	rsv_21		vcc	0	x	x
17:16	RO	NA	0	Reserved	rsv_22		vcc	R	x	x
15	RO ((RW))	NA	1b	Role-based Error Reporting When set to 1, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. 0: Role-based error reporting is not supported. 1: Role-based error reporting is supported. ((For Internal Reference: This chip does NOT fully support Role-Base Error reporting. It implemented the way to change the Non-fatal error to become correctable error in the system. However, the default value is 1 for passing Microsoft WLK test. Microsoft treat the root port support Role-Based Error Reporting as support PCIe 1.1. This bit becomes write-able when D0F5 RxF0[0] is programmed to 1.))	RRBERRP		vcc	1	x	x
14	RO	NA	0	Power Indicator Present When set to 1, this bit indicates that a Power Indicator is implemented on the adapter and is electrically controlled by the component on the adapter using the Power_Indicator_On, Power_Indicator_Blink, and Power_Indicator_Off Messages. It is reserved for root port. Note: According to PCIE GEN3 SPEC, the value read from this bit is undefined.	rsv_23		vcc	0	x	x
13	RO	NA	0	Attention Indicator Present When set to 1, this bit indicates that an Attention Indicator is implemented on the adapter and is electrically controlled by the component on the adapter using the Attention_Indicator_On, Attnetion_Indicator_Blink, and Attention_indicator_Off Messages. It is reserved for root port. Note: According to PCIE GEN3 SPEC, the value read from this bit is undefined.	rsv_24		vcc	0	x	x
12	RO	NA	0	Attention Button Present When set to 1, this bit indicates that an Attention Button is implemented on adapter and is electrically controlled by the component on the adapter. Attention Button press events are reported using the Attention_Button_Pressed Message. It is reserved for root port. Note: According to PCIE GEN3 SPEC, the value read from this bit is undefined.	rsv_25		vcc	0	x	x
11:9	RO ((RW))	NA	000b	Endpoint L1 Acceptable Latency This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering. 000: 1us001: 2us 010: 4us011: 8us 100: 16us101: 32us 110: 64us111: No limit It is reserved for root port. ((For Internal Reference: It is reserved for Root Port and supposed to be always 000b. And this bit becomes write-able when D0F5 RxF0[0] is programmed to 1.))	DAL1AL_		vcc	0	x	x
8:6	RO	NA	0	Endpoint L0s Acceptable Latency This field indicates the acceptable total latency that an Endpoint can withstand due to the transition for L0s state to L0 State. 000: 64ns001: 128ns 010: 256ns011: 512ns 100: 1024ns101: 2us 110: 4us111: No limit It is reserved for root Port.	Rsv_44		vcc	0	x	x
5	RO ((RW))	NA	0	Extended Tag Field Supported This bit indicates the maximum supported size of the tag field as a requester. 0: 5-bit tag field supported. 1: 8-bit tag field supported. ((For Internal Reference: RO/RW through D0F5 RxF0[0].))	*DAXTAGF		vcc	0	x	x
4:3	RO	NA	0	Phantom Functions Supported This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the tag identifier. This field indicates the number of most significant bits of the function number portion of Requester ID that are logically combined with the tag identifier. 00: No function number bits used for Phantom Functions. That is, the Tag field of the requester remain at 8 bits. 01: First MSB of function number in Requester ID used for Phantom Functions. That is, MSB bit can be combined with the transaction Tag to form a 9 bits Tag to track the outstanding transactions. 10: First 2 MSB of function number in Requester ID used for Phantom Functions. That is, 2 MSB bits can be combined with the transaction Tag to form a 10 bits Tag to track the outstanding transactions. 11: All three bits of function number in Requester ID used for Phantom Functions. That is, all 3 function bits can be combined with the transaction Tag to form a 11 bits Tag to track the outstanding transactions. This chip does not support the Phantom Functions.	rsv_26		vcc	0	x	x
2:0	RO ((RW))	NA	000b	Max Payload Size Supported This field indicates the maximum payload size that this root port can support for the upstream write requests. 000: 128 bytes (16 QW) 001: 256 bytes (32 QW) 010: 512 bytes (64 QW) 011: 1024 bytes (128 QW) 100: 2048 bytes (256 QW) 101: 4096 bytes (512 QW) 110, 111: Reserved. ((For Internal Reference: RO/RW through D0F5 RxF0[0].))	DAMPSS_		vcc	000b	x	x

Offset Address: 49-48h (D0F0(D0F2)
Device Control 1Default Value: 0010h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15	RO	NA	0	Reserved	rsv_27		vcc	R	x	x
14:12	RO	NA	0	Max Read Request Size This field sets the maximum Read Request size for the device as a Requestor. 000: 128 bytesOthers: Reserved	DCMRRS_		vcc	0	x	x
11	RW	NA	0	Enable No Snoop 0: Disable1: Enable If this bit is set to 1, the device is permitted to set the No Snoop bit in the Requestor Attributes of the transactions to indicate that it does not require hardware enforced cache coherency.	DCENS		vcc	0	x	x
10	RW	NA	0	Auxiliary Power PM Enable 0: Disable1: Enable This bit when set enables device to draw AUX power independent of PME AUX power.	DCAPPME		vcc	0	x	x
9	RO	NA	0	Phantom Functions Enable	DCPFE		vcc	0	x	x
8	RO/RW	NA	0	Extended Tag Field Enable When Rx44[5] (DAXTAGF) is set to 0, this bit is RO. When Rx44[5] (DAXTAGF) is set to 1, this bit is RW. ((For Internal Reference: This bit is RW when D0F02 Rx44[5] is set to 1.)) @((guardbit=DAXTAGF D0F02 RX44[5]))	DCETFE		vcc	0	x	x
7:5	RW	NA	0	Max Payload Size Maximum TLP payload size. 000: 128bytes001: 256 bytes Others: Reserved	DCMPS_		vcc	000	000	x
4	RW	NA	1b	Enable Relaxed Ordering 0: Disable1: Enable If this bit is set to 1, the device is permitted to set the Relaxed Ordering bit in the Requestor Attributes of the transactions to indicate that it does not require strong write ordering.	DCERO		vcc	1	x	x
3	RW	NA	0	Unsupported Request Reporting Enable 0: Disable1: Enable ((For internal verify reference: @((#TOGGLE=1)) ))	DCURRE		vcc	0	x	x
2	RW	NA	0	Fatal Error Reporting Enable 0: Disable1: Enable For a root port, the report of Fatal errors is internal to the root. No external ERR_FATAL message is generated. ((For internal verify reference: @((#TOGGLE=1)) ))	DCFERE		vcc	0	x	x
1	RW	NA	0	Non-Fatal Error Reporting Enable 0: Disable1: Enable For a root port, the report of Non-Fatal errors is internal to the root. No external ERR_NONFATAL message is generated. ((For internal verify reference: @((#TOGGLE=1)) ))	DCNFERE		vcc	0	x	x
0	RW	NA	0	Correctable Error Reporting Enable 0: Disable1: Enable For a root port, the report of correctable errors is internal to the root. No external ERR_COR message is generated. ((For internal verify reference: @((#TOGGLE=1)) ))	DCCERE		vcc	0	x	x

Offset Address: 4B-4Ah (D0F0(D0F2)
Device Status 1Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:6	RO	NA	0	Reserved	Rsv_4b		vcc	R	x	x
5	RO	NA	0	Transactions Pending This bit when set indicates that the port has issued Non-Posted Requests on its own behalf (using the Requestor ID of the Port) which have not been completed.	DSTP		vcc	0	x	x
4	RO ((RW))	NA	0	AUX Power Detected 0: Not detected1: Detected ((For Internal Reference: RW/RO through D0F5 RxF0[0].))	DSAPD		vcc	0	x	x
3	RO	NA	0	Unsupported Request Detected (TL) 0: Not detected1: Detected	DSURD		vcc	0	x	x
2	RO	NA	0	Fatal Error Detected (TL) 0: Not detected1: Detected	DSFED		vcc	0	x	x
1	RO	NA	0	Non-Fatal Error Detected (TL) 0: Not detected1: Detected	DSNFED		vcc	0	x	x
0	RO	NA	0	Correctable Error Detected (TL) 0: Not detected1: Detected	DSCED		vcc	0	x	x

Offset Address: 4F-4Ch (D0F0(D0F2)
Link Capabilities 1 Default Value: 0A01 BC41h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:24	RO ((RW))	NA	0Ah	Port Number This field indicates the PCI Express Port number for the given PCI Express Link. ((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))	LKPN_		vcc	x	x	x
23:22	RO	NA	0	Reserved	rsv_31		vcc	R	x	x
21	RO ((RW))	NA	0	Link Bandwidth Notification Capability This bit indicates support for the Link Bandwidth Notification status and interrupt mechanism. ((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))	RLBWNTFC		vcc	0b	x	x
20	RO ((RW))	NA	0	Data Link Layer Link Active Reporting Capable This bit indicates support of reporting the DL_Active state of DLCMSM. ((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))	RDL_AR_CAP		vcc	0b	x	x
19	RO ((RW))	NA	0	Surprise Down Error Reporting Capable This bit indicates support of detecting and reporting a Surprise Down error condition. ((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))	RLCASDERC		vcc	0b	x	x
18	RO	NA	0	Clock Power Management	RLCACPM		vcc	0	x	x
17:15	RO ((RW))	NA	011b	L1 Exit Latency This field indicates the L1 exit latency (to L0) for the given PCIe Link. Defined encoding for this latency Tl_L1 are: 000: Tl_L1 < 1us 001: 1us <= Tl_L1< 2us 010: 2us <= Tl_L1 < 4us 011: 4us <= Tl_L1 < 8us 100: 8us <= Tl_L1 < 16us 101: 16us <= Tl_L1 < 32us 110: 32us <= Tl_L1 < 64us 111: 64us <= Tl_L1 ((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))	LKL1EL_		vcc	x	x	x
14:12	RO((RW))	NA	011b	L0s Exit Latency This field indicates the L0s exit latency (to L0) for the given PCIe Link. Read return value is from following registers: D2F4 RxE1[2:0] when PE3 in 2.5G/Ts speed. D2F4 RxE2[2:0] when PE3 in 5.0G/Ts speed.	LKL0SE_		vcc	x	x	x
11:10	RO ((RW))	NA	11b	Active State Link PM (ASPM) Support 11b: L0s and L1 supported. ((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))	LKAPMS_		vcc	11b	x	x
9	RO ((RW))	NA	0	Maximum Link Width Bit 5	LKMLW_5		vcc	0	x	x
8	RO ((RW))	NA	0	Maximum Link Width Bit 4	LKMLW_4		vcc	0	x	x
7	RO ((RW))	NA	0	Maximum Link Width Bit 3	LKMLW_3		vcc	0	x	x
6	RO ((RW))	NA	1b	Maximum Link Width Bit 2	LKMLW_2		vcc	1b	x	x
5	RO ((RW))	NA	0	Maximum Link Width Bit 1	LKMLW_1		vcc	x	x	x
4	RO ((RW))	NA	0	Maximum Link Width Bit 0	LKMLW_0		vcc	x	x	x
3	RO ((RW))	NA	0	Max Link Speed Bit 3 Max Link Speeds – This field indicates the supported maximum Link speed(s) of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed. Defined encodings are: 0001b: Supported Link Speeds Vector field bit 0. 0010b: Supported Link Speeds Vector field bit 1. 0011b: Supported Link Speeds Vector field bit 2. 0100b: Supported Link Speeds Vector field bit 3. 0101b: Supported Link Speeds Vector field bit 4. 0110b: Supported Link Speeds Vector field bit 5. 0111b: Supported Link Speeds Vector field bit 6.	LKMAXLS_ 3		vcc	0	x	x
2	RO ((RW))	NA	0	Max Link Speed Bit 2	LKMAXLS_ 2		vcc	0	x	x
1	RO ((RW))	NA	0b	Max Link Speed Bit 1	LKMAXLS_ 1		vcc	0b	x	x
0	RO ((RW))	NA	1b	Max Link Speed Bit 0	LKMAXLS_ 0		vcc	1b	x	x

Offset Address: 51-50h (D0F0(D0F2)
Link Control 1Default Value: 0040h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:12	RO	NA	0	Reserved	rsv_32		vcc	R	x	x
11	RW	NA	0	Enable Link Autonomous Bandwidth Interrupt 0: Disable. 1: Enable the generation of an interrupt to indicate that the autonomous bandwidth status bit (Rx53[7] (RLATNMBW) ) has been set. ((For internal verify reference: @((#TOGGLE=1)) ))	RLABITEN		vcc	0	x	x
10	RW	NA	0	Enable Link Bandwidth Management Interrupt 0: Disable. 1: Enable the generation of an interrupt to indicate that the link bandwidth management status bit (Rx53[6] (RLBWMNGT) ) has been set. ((For internal verify reference: @((#TOGGLE=1)) ))	RLBMITEN		vcc	0	x	x
9	RW	NA	0	Hardware Autonomous Width Control 0: Hardware can change the link width because of correcting unreliable link operations or power saving issue. 1: Hardware can change the link width only because of correcting unreliable link operations.	RHATNMWD		vcc	0	x	0
8	RO	NA	0	Enable Clock Power Management 0: Disable1: Enable	RLCOCPMEN		vcc	0	x	x
7	RW	NA	0	Extended Synch 0: FCU timer limit is 30us. No. of FTS ordered set to be transmitted from L0s to L0 is N_FTS. No. of TS1 to be transmitted in Recovery.RcvrLock is not limited. 1: FCU timer limit is 120us. No. of FTS ordered set to be transmitted from L0s to L0 is 4096. No. of TS1 to be transmitted in Recovery.RcvrLock is at least 1024.	LCES		vcc	0	0	x
6	RW	NA	1b	Common Clock Configuration 0: Indicates that this port and the component on the opposite end of the link are operating with asynchronous reference clock. 1: Indicates that this port and the component on the opposite end of the link are operating with a distributed common reference clock.	LCCCC		vcc	x	x	x
5	RO	NA	0	Retrain Link Link retrain is initiated by writing 1 to this bit. This will direct the Physical Layer LTSSM to the Recovery state. Hardware will clear this bit to 0 when complete.	LCRL		vcc	0	x	x
4	RW	NA	0	Link Disable 0: Enable the link1: Disable the link	LCLD		vcc	0	x	x
3	RO ((RW))	NA	0	Read Completion Boundary 0: 64 bytes1: 128 bytes ((For Internal Reference: RO/RW through D0F5 RxF0[0].))	LCRCB		vcc	0	x	x
2	RO	NA	0	Reserved	rsv_33		vcc	R	x	x
1:0	RW	NA	00b	Link Active State PM (ASPM) Control 00: Disable 01: Enable L0s entry 10: Enable L1 entry 11: Enable L0s and L1 entry	LCAPMS_		vcc	00b	00b	00b

Offset Address: 53-52h (D0F0(D0F2)
Link Status 1Default Value: 1000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15	RO	NA	0	Link Autonomous Bandwidth Status This bit is set to 1b to indicate that hardware has autonomously changed link speed or width, without the port transitioning through DL_Down status, for reasons other than attempt to correct unreliable link operation.	*RLATNMBW		vcc	0	x	x
14	RO	NA	0	Link Bandwidth Management Status This bit is asserted when: LTSSM transits from Recovery to L0. Link speed is changed. Link width is changed.	RLBWMNGT		vcc	0	x	x
13	RO	NA	0	Data Link Layer Link Active 0: Inactive1: Active	*DL_ACTIVE		vcc	x	x	x
12	RO ((RW))	NA	1b	Slot Clock Configuration 0: Use an independent clock irrespective of the presence of a reference on the connector. 1: Use the same physical reference clock that the platform provides on the connector. ((For Internal Reference: RO/RW through D0F5RxF0[0].))	LSSCC		vcc	x	x	x
11	RO	NA	0	Link Training This bit indicate that Link training is in progress (Physical Layer LTSSM is in Configuration or Recovery state) or the Retrain Link bit is set but Link training has not yet begun. Hardware clears this bit once Link training is complete.	LSLT		vcc	0	x	x
10	RO	NA	0	Training Error Set when a Link training error occurs. Cleared by hardware upon successfully training of the Link to the L0 Link state.	LSTE		vcc	0	x	x
9	RO	NA	0	Negotiated Link Width Bit 5 Hardwired to 0.	tbd_28		vcc	0	x	x
8:4	RO((RW))	NA	0	Negotiated Link Width Bits[4:0] Default value set by hardware initial. 00001: x100010: x2 00100: x401000: x8 01000: x16 Others: Reserved	LSNLW_		vcc	0	x	x
3:0	RO((RW))	NA	0	Current Link Speed Current Link Speed – This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed. Defined encodings are: 0001: Supported Link Speeds Vector field bit 0. 0010: Supported Link Speeds Vector field bit 1. 0011: Supported Link Speeds Vector field bit 2. 0100: Supported Link Speeds Vector field bit 3. 0101: Supported Link Speeds Vector field bit 4. 0110: Supported Link Speeds Vector field bit 5. 0111: Supported Link Speeds Vector field bit 6. All other encodings are Reserved. The value in this field is undefined when the Link is not up.	LSLS_		vcc	0	x	x

Offset Address: 57-54h (D0F0(D0F2)
Slot Capabilities 1Default Value: 0000 0020h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:19	RO ((RW))	NA	0	Physical Slot Number; Reserved Physical slot number attached to the port. ((For Internal Reference: RO/RW through D0F5 RxF0[0].))	SLPSN_		vcc	0	x	x
18	RO ((RW))	NA	0	No Command Completed Support 0: Not supported1: Supported ((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))	RSCANCCS		vcc	0	x	x
17	RO ((RW))	NA	0	Electromechanical Interlock Present 0: Not present1: Present ((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))	RSCAEMIP		vcc	0	x	x
16:15	RO ((RW))	NA	00b	Slot Power Limit Scale Specify the scale used for the Slot Power Limit Value. Range of values: 00: 1.0x01: 0.1x 10: 0.01x11: 0.001x This register must be implemented if the Slot Implemented bit is set. ((For Internal Reference: Write to the field causes the Port to send the Set_Slot_Power_Limit message. RO/RW through D0F5 RxF0[0].))	RSPLS_		vcc	0	x	x
14:7	RO ((RW))	NA	0	Slot Power Limit Value In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. This register must be implemented if the Slot Implemented bit is set. ((For Internal Reference: Write to the field causes the Port to send the Set_Slot_Power_Limit message. RO/RW through D0F5 RxF0[0].))	RSPLV_		vcc	0	x	x
6	RO ((RW))	NA	0	Hot-Plug Capable 1b indicates that this slot is capable of supporting hot-plug operations. ((For Internal Reference: RO/RW through D0F5 RxF0[0].)) ((For internal verify reference: @((#TOGGLE=1)) ))	SCHP_CAP		vcc	0	x	x
5	RO ((RW))	NA	1b	Hot-Plug Surprise 1b indicates that an adapter present in this slot may be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow such removal without impact on successive software operation. ((For Internal Reference: RO/RW through D0F5 RxF0[0].)) ((For internal verify reference: @((#TOGGLE=1)) ))	SCHPS		vcc	1	x	x
4	RO ((RW))	NA	0	Power Indicator Present When set to 1b, this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. ((For Internal Reference: RO/RW through D0F5 RxF0[0].)) ((For internal verify reference: @((#TOGGLE=1)) ))	SCPIP		vcc	0	x	x
3	RO ((RW))	NA	0	Attention Indicator Present When set to 1b, this bit indicates that an Attention Indicator is electrically controlled by the chassis. ((For Internal Reference: RO/RW through D0F5 RxF0[0].)) ((For internal verify reference: @((#TOGGLE=1)) ))	SCAIP		vcc	0	x	x
2	RO	NA	0	MRL Sensor Present Reserved	rsv_36		vcc	0	x	x
1	RO	NA	0	Power Controller Present Reserved	rsv_37		vcc	0	x	x
0	RO ((RW))	NA	0	Attention Button Present When set to 1b, this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. ((For Internal Reference: RO/RW through D0F5 RxF0[0].)) ((For internal verify reference: @((#TOGGLE=1)) ))	SCABP		vcc	0	x	x

Offset Address: 59-58h (D0F0(D0F2)
Slot Control 1Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:13	RO	NA	0	Reserved	rsv_39		vcc	R	x	x
12	RW	NA	0	Enable Data Link Layer State Change 0: Disable1: Enable If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed. ((For internal verify reference: @((#TOGGLE=1)) ))	RDLSCHGEN		vcc	0	x	x
11	RO	NA	0	Electromechanical Interlock Control 0: Disable1: Enable	RSCOEMIC		vcc	0	x	x
10	RW	NA	0	Power Controller Control 0: Power on1: Power off If a power controller is implemented, this bit when written sets the power state of the slot per the defined encodings. If the Power Controller Implemented field in the Slot Capabilities register is set to 0b, then writes to this field have no effect and the read value of this field is undefined.	SCPCC		vcc	0	x	x
9:8	RO/RW	NA	00b	Power Indicator Control If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write,even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. Defined encodings are: 00: Reserved01: On 10: Blink11: Off This bit is RW when D0F02 Rx54[4] is set to 1. Note: The default value of this field must be one of the non-Reserved values. @((guardbit = SCPIP D0F02 RX54[4])) ((For Internal Reference: 00: Reserved01: On 10: Blink11: Off Writes to this field cause the port to send the appropriate POWER_INDICATOR_* Message.))	SCPIC_		vcc	0	x	x
7:6	RO/RW	NA	00b	Attention Indicator Control If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. Defined encodings are: 00: Reserved01: On 10: Blink11: Off This bit is RW when D0F02 Rx54[3] is set to 1. Note: The default value of this field must be one of the non-Reserved values. @((guardbit = SCAIP D0F20 RX54[3])) ((For Internal Reference: 00: Reserved01: On 10: Blink11: Off Writes to this field cause the ort to send the appropriate ATTENTION_INDICATOR_* Message.))	SCAIC_		vcc	0	x	x
5	RO/RW	NA	0	Enable Hot-Plug Interrupt 0: If the Hot Plug Capable field in the Slot Capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b. 1: When set to 1b, this bit enables generation of an interrupt on enabled hot-plug events. This bit is RW when D0F02 Rx54[6] is set to 1. @((guardbit = SCHP_CAP D0F02 RX54[6])) ((For Internal Reference: 0: Disable1: Enable his bit when set enables generation of Hot-Plug interrupt on enabled Hot-Plug events.))	SCHPIE		vcc	0	x	x
4	RW	NA	0	Enable Command Completed Interrupt 0: If Command Completed notification is not supported, this bit must be hardwired to 0b. 1: When set to 1b, this bit enables software notification when a hot-plug command is completed by the Hot-Plug Controller. ((For Internal Reference: 0: Disable1: Enable This bit when set enables the generation of Hot-Plug interrupt when a command is completed by the Hot-Plug controller.))	SCCCIE		vcc	0	x	x
3	RW	NA	0	Enable Presence Detect Change When set to 1b, this bit enables software notification on a presence detect changed event. ((For Internal Reference: 0: Disable1: Enable This bit when set enables the generation of Hot-Plug interrupt or WakeuPEvent on a presence detect changed event.))	SCPDCE		vcc	0	x	x
2	RO	NA	0	Enable MRL Sensor Change Reserved ((For Internal Reference: 0: Disable1: Enable ))	rsv_40		vcc	0	x	x
1	RO	NA	0	Enable Power Fault Detected Reserved ((For Internal Reference: 0: Disable1: Enable ))	rsv_41		vcc	0	x	x
0	RO/RW	NA	0	Enable Attention Button Pressed When set to 1b, this bit enables software notification on an attention button pressed event. This bit is RW when D0F02 Rx54[0] is set to 1. ((For Internal Reference: 0: Disable1: Enable This bit when set enables the generation of Hot-Plug interrupt or WakeuPEvent on an Attention Button pressed event.)) @((guardbit = SCABP D0F02 Rx54[0]))	SCABPE		vcc	0	x	x

Offset Address: 5B-5Ah (D0F0(D0F2)
Slot Status 1Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:9	RO	NA	0	Reserved	rsv_42		vcc	R	x	x
8	RO	NA	0	Data Link Layer State Changed 0: No state changed1: State changed	RDLSCHG		vcc	0	x	x
7	RO	NA	0	Electromechanical Interlock Status	RSSEMIS		vcc	0	x	x
6	RO	NA	0	Presence Detect State 0: Slot empty 1: Card present in slot	SPDCST		vcc	0	x	x
5	RO	NA	0	MRL (Manually Operated Retention Latch) Sensor State Reserved	rsv_43		vcc	0	x	x
4	RO	NA	0	Command Completed 0: Not completed1: Completed	SSCC		vcc	0	x	x
3	RO	NA	0	Presence Detect Change 0: Not changed1: Changed	SPDC		vcc	0	x	x
2	RO	NA	0	MRL Sensor Change 0: Not changed1: Changed	tbd_29		vcc	0	x	x
1	RO	NA	0	Power Fault Detected 0: Not changed1: Changed	tbd_30		vcc	0	x	x
0	RO	NA	0	Attention Button Pressed 0: No state changed1: State changed	SSABP		vcc	0	x	x

Offset Address: 5D-5Ch (D0F0(D0F2)
Root ControlDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:5	RO	NA	0	Reserved	Rsv_5c_5		vcc	R	x	x
4	RW	NA	0	Enable CRS Software Visibility 0: Disable. 1: Enable the root port to return Configuration Request Retry Status (CRS) completion status to software. ((For internal verify reference: @((#TOGGLE=1)) ))	RCCRSSVE		vcc	0	x	x
3	RW	NA	0	Enable PME Interrupt 0: Disable. 1: Enable interrupt generation upon receipt of a PME message as reflected in the PME status register bit. A PME interrupt is also generated if the PME status register bit is set when this bit is set from a cleared state.	RCPMEIE		vcc	0	x	x
2	RW	NA	0	Enable System Error on Fatal Error 0: Disable. 1: Enable generation of a System Error if a Fatal Error (ERR_FATAL) is reported by any of the devices in the hierarchy associated with the root port, or by the root Port itself.	RCSEFEE		vcc	0	x	x
1	RW	NA	0	Enable System Error on Non-Fatal Error 0: Disable. 1: Enable generation of a System Error if a Non-Fatal Error (ERR_NONFATAL) is reported by any of the devices in the hierarchy associated with the root port, or by the root port itself.	RCSENFEE		vcc	0	x	x
0	RW	NA	0	Enable System Error on Correctable Error 0: Disable. 1: Enable generation of a System Error if a Correctable Error (ERR_COR) is reported by any of the devices in the hierarchy associated with the root port, or by the root port itself.	RCSECEE		vcc	0	x	x

Offset Address: 5F-5Eh (D0F0(D0F2)
Root CapabilitiesDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:1	RO	NA	0	Reserved	rsv_44_5e		vcc	R	x	x
0	RO ((RW))	NA	0	Configuration Request Retry Status (CRS) Software Visibility 0: Disable. The Root Port cannot return CRS completion status to software. 1: Enable. The Root Port will return CRS completion status to software. ((For Internal Reference: RO/RW through D0F5 RxF0[0].)) ((For internal verify reference: @((#TOGGLE=1)) ))	RSCRSSFV		vcc	0	x	x

Offset Address: 63-60h (D0F0(D0F2)
Root StatusDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:18	RO	NA	0	Reserved	rsv_45		vcc	R	x	x
17	RO	NA	0	PME Pending 0: No pending PME. 1: Indicates another PME is pending when the PME Status (bit 16) is set.	RSPP		vcc	0	x	x
16	RO	NA	0	PME Status Indicates that the PME is asserted by the Requestor ID indicated in PME Requestor ID (bits[15:0]).	RSPS		vcc	0	x	x
15:0	RO	NA	0	PME Requester ID The Requestor ID of the last PME Requestor.	RSPRID_		vcc	0	x	x

Offset Address: 67-64h (D0F0(D0F2)
Device Capabilities 2Default Value: 0000 0010h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:20	RO	NA	0	Reserved	Rsv_64_6		vcc	R	x	x
19:18	RO ((RW))	NA	0	OBFF Supported 00: OBFF not supported. 01: OBFF supported using Message signaling only. 10: OBFF supported using WAKE# signaling only. 11: OBFF supported using WAKE# and Message signaling.	ROBFFSP_		vcc	0	x	x
17:12	RO	NA	0	Reserved	Rsv_64_12		vcc	R	x	x
11	RO ((RW))	NA	0	LTR Mechanism Supported A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism capability.	RLTRSP		vcc	0	x	x
10:6	RO	NA	0	Reserved	Rsv_64_10		vcc	x	x	x
5	RO ((RW))	NA	0	Alternative Routing-ID Interpretation (ARI) Forwarding Supported 0: Not supported1: Supported ARI is used to increase the number of functions supported by single device.	RARISP		vcc	0	x	x
4	RO ((RW))	NA	1b	Completion Timeout Disable Supported 0: Not support Completion Timeout Disable. 1: Support Completion Timeout Disable. ((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))	tbd_31		vcc	1	x	x
3:0	RO	NA	0	Completion Timeout Ranges Supported 0: Not supported1: Supported ((For Internal Reference: The timeout value is in the range from 50us to 50ms, compliant with PCIe 1.1))	tbd_32		vcc	0	x	x

Offset Address: 69-68h (D0F0(D0F2)
Device Control 2Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15	RO	NA	0	Reserved	rsv_46		vcc	R	x	x
14:13	RW	NA	0	OBFF Enable 00: Disabled 01: Enabled using Message signaling [Variation A] 10: Enabled using Message signaling [Variation B] 11: Enabled using WAKE# signaling	ROBFFEN_		vcc	0	x	x
12:11	RO	NA	0	Reserved	Rsv_68_11		vcc	R	x	x
10	RW	NA	0	LTR Mechanism Enable When Set to 1b, this bit enables the Latency Tolerance Reporting (LTR) mechanism	RLTREN		vcc	0	x	x
9:6	RO	NA	0	Reserved	Rsv_68_6		vcc	R	x	x
5	RO/RW	NA	0	Enable ARI Forwarding 0: Disable. Check device number being 0 when turning downstream Type1 configuration to Type 0 configuration. 1: Enable. Never check device number when turning downstream Type1 configuration to Type 0 configuration. This bit is RW when D0F02 Rx64[5] is set to 1. ((For Internal Reference: Internal design guideline Default value of this bit is 0b. Must be hardwired to 0b if the ARI Forwarding Supported bit (D0F0(D0F2 Rx64[5]) is 0b.)) @((guardbit=RARISP D0F02 RX64[5]))	RARIEN		vcc	0	x	x
4	RW	NA	0	Completion Timeout Disable Control 0: Enable completion timeout function. 1: Disable completion timeout function.	*RDISCPLTM		vcc	0	0	x
3:0	RO	NA	0	Completion Timeout Value ((For Internal Reference: Not support completion timeout programmability then hardwire this field to 0000b.))	tbd_33		vcc	0	x	x

Offset Address: 6B-6Ah (D0F0(D0F2)
Device Status 2Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RO	NA	0	Reserved	rsv_47		vcc	R	x	x

Offset Address: 6F-6Ch (D0F0(D0F2)
Link Capabilities 2Default Value: 0001 0202h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:19	RO	NA	0	Reserved	rsv_6c_31		vcc	R	x	x
18	RO ((RW))	NA	0	Lower SKP OS Reception Supported Speeds Vector If this field is non-zero, it indicates that the Port, when operating at the indicated speed(s) supports SRIS and also supports receiving SKP OS at the rate defined for SRNS while running in SRIS. Bit definitions within this field are: Bit 0: 2.5 GT/sBit 1: 5.0 GT/s Bit 2: 8.0 GT/sBits 6:3: RsvdP	RLOW_SKP_REC_SUPPORT_2		vcc	x	x	X
17	RO ((RW))	NA	0	Lower SKP OS Reception Supported Speeds Vector	RLOW_SKP_REC_SUPPORT_1		vcc	x	x	X
16	RO ((RW))	NA	1b	Lower SKP OS Reception Supported Speeds Vector	RLOW_SKP_REC_SUPPORT_0		vcc	x	x	X
15:12	RO	NA	0	Reserved	rsv_6c_15		vcc	R	x	x
11	RO ((RW))	NA	0	Lower SKP OS Generation Supported Speeds Vector If this field is non-zero, it indicates that the Port, when operating at the indicated speed(s) supports SRIS and also supports software control of the SKP Ordered Set transmission scheduling rate. Bit definitions within this field are: Bit 0: 2.5 GT/sBit 1: 5.0 GT/s Bit 2: 8.0 GT/s	RLOW_SKP_GEN_SUPPORT_2		vcc	x	x	x
10	RO ((RW))	NA	0	Lower SKP OS Generation Supported Speeds Vector	RLOW_SKP_GEN_SUPPORT_1		vcc	x	x	X
9	RO ((RW))	NA	1b	Lower SKP OS Generation Supported Speeds Vector	RLOW_SKP_GEN_SUPPORT_0		vcc	x	x	X
8	RO	NA	0	CrossLink Supported 0 indicates the RP does not support CrossLink.	Rsv_6c_8		vcc	0	x	x
7	RO	NA	0	Supported Link Speed Vector Bit 6 Reserved	LKMLS_ 6		vcc	0	x	x
6	RO	NA	0	Supported Link Speed Vector Bit 5 Reserved	LKMLS_ 5		vcc	0	x	x
5	RO	NA	0	Supported Link Speed Vector Bit 4 Reserved	LKMLS_ 4		vcc	0	x	x
4	RO	NA	0	Supported Link Speed Vector Bit 3 Reserved	LKMLS_ 3		vcc	0	x	x
3	RO ((RW))	NA	0	Supported Link Speed Vector Bit 2, 8.0GT/s	LKMLS_2		vcc	0	x	x
2	RO ((RW))	NA	0	Supported Link Speed Vector Bit 1, 5.0GT/s	LKMLS_1		vcc	0b	x	x
1	RO ((RW))	NA	1b	Supported Link Speed Vector Bit 0, 2.5 GT/s	LKMLS_ 0		vcc	1b	x	x
0	RO	NA	0	Reserved	rsv_6c_0		vcc	R	x	x

Offset Address: 71-70h (D0F0(D0F2)
Link Control 2Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:12	RW	NA	0	Compliance Preset / De-emphasis For 8.0 GT/s Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. For 5.0 GT/s Data Rate: This bit field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Defined Encodings are: 0001b: -3.5 dB 0000b: -6 dB	CMPPSDEEMPHS_		vcc	0	x	x
11	RW	NA	0	SKP Ordered Set (SOS) Transmission between Compliance Patterns 0: No SOS is sending between the (modified) compliance patterns. 1: The LTSSM is sending SOS periodically in between the (modified) compliance patterns.	RCMPSOS		vcc	0	x	x
10	RW	NA	0	Modified Compliance Pattern Set Bit 0: Device transmits normal compliance pattern if LTSSM enters Polling.Compliance state. 1: Device transmits modified compliance pattern if LTSSM enters Polling.Compliance state.	PMDCMPSET		vcc	0	x	x
9	RW	NA	0	Transmit Voltage Margin Setting Bits [9:7] 000: Normal operating range. 001: 800-1200 mV for full swing and 400-700 mV for half-swing. 010 ~ (n-1): Values must be monotonic with a non-zero slope. The value of n must be greater than 3 and less than 7. At least two of these must be below the normal operating range of n: 200-400 mV for full-swing and 100-200 mV for half-swing. n ~ 111: Reserved.	TXMGN _2		vcc	0	x	x
8	RW	NA	0	Transmit Voltage Margin Setting Bits [9:7] 000: Normal operating range. 001: 800-1200 mV for full swing and 400-700 mV for half-swing. 010 ~ (n-1): Values must be monotonic with a non-zero slope. The value of n must be greater than 3 and less than 7. At least two of these must be below the normal operating range of n: 200-400 mV for full-swing and 100-200 mV for half-swing. n ~ 111: Reserved.	TXMGN_1		vcc	0	x	x
7	RW	NA	0	Transmit Voltage Margin Setting Bits [9:7] 000: Normal operating range. 001: 800-1200 mV for full swing and 400-700 mV for half-swing. 010 ~ (n-1): Values must be monotonic with a non-zero slope. The value of n must be greater than 3 and less than 7. At least two of these must be below the normal operating range of n: 200-400 mV for full-swing and 100-200 mV for half-swing. n ~ 111: Reserved.	TXMGN_0		vcc	0	x	x
6	RO ((RW))	NA	0	Selectable De-emphasis 0: -6 db1: -3.5db When the link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an upstream component.	SELDEEMPHS		vcc	0	x	x
5	RW	NA	0	Disable Hardware Autonomous Speed 0: Enable hardware autonomous speed negotiation. 1: Disable hardware autonomous speed negotiation.	RHATNMSD		vcc	0	x	0
4	RW	NA	0	Enter Compliance 0: Normal negotiation. 1: Force to polling.compliance.	PCMPSET		vcc	0	x	x
3	RW	NA	0	Target Link Speed Bit 3	LKTGLS_3		vcc	0	0	0
2	RW	NA	0	Target Link Speed Bit 2	LKTGLS_ 2		vcc	0	0	0
1	RW	NA	0	Target Link Speed Bit 1	LKTGLS_ 1		vcc	0	0	0
0	RW	NA	0	Target Link Speed Bit 0	LKTGLS_ 0		vcc	0	0	0

Offset Address: 73-72h (D0F0(D0F2)
Link Status 2Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:6	RO	NA	0	Reserved	rsv_49		vcc	R	x	x
5	RO	NA	0	Request the Link Equalization Process This bit is Set to 1 by hardware to request the Link equalization process to be performed on the Link.	EQREQ		vcc	x	x	x
4	RO	NA	0	Transmitter Equalization Procedure Completed -Phase 3 1: Phase 3 of the Transmitter Equalization procedure has successfully completed.	EQCOMPLE3		vcc	x	x	x
3	RO	NA	0	Transmitter Equalization Procedure Completed -Phase 2 1: Phase 2 of the Transmitter Equalization procedure has successfully completed.	EQCOMPLE2		vcc	x	x	x
2	RO	NA	0	Transmitter Equalization Procedure Completed -Phase 1 1: Phase 1 of the Transmitter Equalization procedure has successfully completed.	EQCOMPLE1		vcc	x	x	x
1	RO	NA	0	Transmitter Equalization Procedure Completed 1: Transmitter Equalization procedure has completed.	EQCOMPLE		vcc	x	x	x
0	RO	NA	0	Current Link De-emphasis Level 0: -6 db1: -3.5db	CURDEEMPHS		vcc	x	x	x

Offset Address: 74-7Fh (D0F0(D0F2) – Reserved

Reserved for PCIe Slot Capabilities 2, Slot Control 2 and Slot Status 2 Register

Reserved for PCI Power Management Capability Structure Registers (80-87h)

Offset Address: 83-80h (D0F0(D0F2)
Power Management CapabilitiesDefault Value: C822 0001h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:27	RO ((RW))	NA	11001b	PME Support 0: Not supported1: Supported Bit 31, 30 and 27 are set to 1b (PME Message will be forwarded). ((For Internal Reference: RW when D0F5 RxF0[0]=1.))	PMCPME_		vcc	19h	x	x
26	RO ((RW))	NA	0	D2 Support 0: Not supported1: Supported ((For Internal Reference: RW when D0F5 RxF0[0]=1.))	PMCD2S		vcc	0	x	x
25	RO ((RW))	NA	0	D1 Support 0: Not supported1: Supported ((For Internal Reference: RW when D0F5 RxF0[0]=1.))	PMCD1S		vcc	0	x	x
24:22	RO ((RW))	NA	0	AUX Current ((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))	PMCAUXC_		vcc	0	x	x
21	RO ((RW))	NA	1b	Device Specific Initialization Do not program. ((For Internal Reference: RW when D0F5 RxF0[0]=1.))	PMCDSI		vcc	1	x	x
20:19	RO	NA	0	Reserved	rsv_53		vcc	R	x	x
18:16	RO	NA	010b	Version	tbd_34		vcc	010b	x	x
15:8	RO((RW))	NA	00h	Next Capability Pointer	tbd_35		vcc	00h	x	x
7:0	RO	NA	01h	Capability ID 01h indicates extended capability ID for the advanced error reporting capability.	tbd_36		vcc	01h	x	x

Offset Address: 87-84h (D0F0(D0F2)
Power Management Status / ControlDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:24	RO	NA	0	Power Management Data	tbd_37		vcc	R	x	x
23	RO ((RW))	NA	0	Enable Bus Power / Clock Control 0: Disable1: Enable ((For Internal Reference: RO/RW through D0F5 RxF0[0].))	tbd_38		vcc	x	x	x
22	RO ((RW))	NA	0	B2 / B3 Support ((For Internal Reference: RO/RW through D0F5 RxF0[0].))	tbd_39		vcc	x	x	x
21:16	RO	NA	0	Reserved	rsv_54		vcc	R	x	x
15	RO	NA	0	PME Status This bit’s setting is not modified by hot, warm or cold reset.	PMESD		vcc	0	x	x
14:13	RO	NA	0	Data Scale	tbd_40		vcc	0	x	x
12:9	RO	NA	0	Data Select	tbd_41		vcc	0	x	x
8	RW	NA	0	PME Enable 0: Disable1: Enable This bit’s setting is not modified by hot, warm or cold reset. ((For internal verify reference: @((#TOGGLE=1)) ))	PMEEN		vcc	0	x	x
7:2	RO	NA	0	Reserved	rsv_55		vcc	R	x	x
1:0	RW	NA	00b	Power State 00: D001: D1 10: D211: D3 hot	PWSD_		vcc	0	x	x

Reserved Registers (88-8Fh)

Offset Address: 8B-88h (D0F0(D0F2)
Reserved ((Internal-RW))Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RW	NA	0	Reserved ((Writing 1 or 0 to these bits does not change any behavior of this chip.))	Rx88[31:0]		vcc	0	x	x

Offset Address: 8F-8Ch (D0F0(D0F2)
Reserved ((Internal-RW))Default Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:0	RW	NA	0	Reserved ((Writing 1 or 0 to these bits does not change any behavior of this chip.))	Rx8C[31:0]		vcc	0	x	x

@((REG_GROUP (System SVADDVAD Control): RANGE=(90h,3FFh)))

System View Address Decode (90-3FFh)

SVADLimit = highest SVAD limit address

SVAD limit address = N * 256M - 1
MemLimit +1 = highest SVAD limit target to memory(RTOPA)
MemLimit +1 = N * 256M
B4GMemLimit +1 = Below 4G highest memory limit(RLOWTOPA)

B4GMemLimit +1 = N * 256M
B4GMMIOBase = min(MMIOB2G,MMIO2T4G)
Offset Address: 93-90h (D0F2)
MMIOCFG decoderDefault Value: 0nnnnnnnh

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	NA	0	RDID_RID_LOCK_D0F2 ((For Internal Reference: DID_RID_lock_bit 0: DeviceID, RevisionID andRDID_RID_LOCK_D0F2 is RW; 1: DeviceID, RevisionID and RDID_RID_LOCK_D0F2 is RO; @((#control_lock = lock_portRDID_RID_LOCK_D0F2)) ))	RDID_RID_LOCK_D0F2		vcc	0	x	x
30	RWL	NA	0	RSVAD_LOCK This is a lock bit for the related register “SVAD”: 1: When this((Lock_bit)) is set to 1, the SVAD related register is RO. 0: When this((Lock_bit)) is set to 0, the SVADrelated regisrer is RW ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) @((#control_txt_lock = LOCK_SMRAM)) @((#control_txt_unlock = UNLOCK_SMRAM)) )) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_LOCK		vcc	x	x	x
29	RWL	NA	0	RVID_DID_LOCK_D0F2 ((For Internal Reference: VID_DID_lock_bit 0: VendorID andRVID_DID_LOCK_D0F2 is RW; 1: VendorID and RVID_DID_LOCK_D0F2 is RO; @((#control_lock = lock_portRVID_DID_LOCK_D0F2)) @((#control_default = NB_VID_DID_LOCK)) ))	RVID_DID_LOCK_D0F2		vcc	x	x	x
28	RWL	NA	0	C2M_Tseg_range _Protection_LOCK_D0F2 0: C2M Tseg range Protection control is RW; 1: C2M Tseg range Protection control is RO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock=lock_portRSVAD_LOCK )) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVID_TSEGPRT		vcc	x	x	x
27:8	RWL	RO	ROMSIP	MMIOCFG base This 14 bits are MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[61:48]))？？？？ ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFGBASE[45:26]		vcc	x	x	x
7:3	RWL	RO	ROMSIP	MMIOCFG SN0base This 5 bits are sub node0 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N0_BASE[27:23]		vcc	x	x	x
2	RWL	RO	0	RCLASS_CODE_LOCK_D0F2 ((For Internal Reference: ClassCode_lock_bit 0: ClassCodeand RCLASS_CODE_LOCK_D0F2 is RW; 1: ClassCode and RCLASS_CODE_LOCK_D0F2 is RO; @((#control_lock = lock_portRCLASS_CODE_LOCK_D0F2)) ))	RCLASS_CODE_LOCK_D0F2		vcc	x	x	x
1:0	RO	NA	0	Reserved	Rx90[1:0]		vcc	x	x	x

Offset Address: 97-94h (D0F2)
MMIOCFG decoderDefault Value:nnnn nnnnh

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:27	RWL	RO	ROMSIP	MMIOCFG SN1 base This 5 bits are sub node1 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N1_BASE[27:23]		vcc	x	x	x
26:22	RWL	RO	ROMSIP	MMIOCFG SN2 base This 5 bits are sub node2 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N2_BASE[27:23]		vcc	x	x	x
21:17	RWL	RO	ROMSIP	MMIOCFG SN3 base This 5 bits are sub node3 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N3_BASE[27:23]		vcc	x	x	x
16:12	RWL	RO	ROMSIP	MMIOCFG SN4 base This 5 bits are sub node4 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N4_BASE[27:23]		vcc	x	x	x
11:7	RWL	RO	ROMSIP	MMIOCFG SN5 base This 5 bits are sub node5 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N5_BASE[27:23]		vcc	x	x	x
6:2	RWL	RO	ROMSIP	MMIOCFG SN6 base This 5 bits are sub node6 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N6_BASE[27:23]		vcc	x	x	x
1:0	RO	NA	0	Reserved	Rx94[1:0]		vcc	x	x	x

Offset Address: 9B-98h (D0F2)
MMIOCFG decoderDefault Value: nnnn nnnnh

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:27	RWL	RO	ROMSIP	MMIOCFG SN7 base This 5 bits are sub node7 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N7_BASE[27:23]		vcc	x	x	x
26:22	RWL	RO	ROMSIP	MMIOCFG SN8 base This 5 bits are sub node8 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N8_BASE[27:23]		vcc	x	x	x
21:17	RWL	RO	ROMSIP	MMIOCFG SN9 base This 5 bits are sub node9 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N9_BASE[27:23]		vcc	x	x	x
16:12	RWL	RO	ROMSIP	MMIOCFG SN10 base This 5 bits are sub node10 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N10_BASE[27:23]		vcc	x	x	x
11:7	RWL	RO	ROMSIP	MMIOCFG SN11 base This 5 bits are sub node11 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N11_BASE[27:23]		vcc	x	x	x
6:2	RWL	RO	ROMSIP	MMIOCFG SN12 base This 5 bits are sub node12 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N12_BASE[27:23]		vcc	x	x	x
1:0	RO	NA	0	Reserved	Rx98[1:0]		vcc	x	x	x

Offset Address: 9F-9Ch (D0F2)
MMIOCFG and MMIOB2G decoderDefault Value: nnnn 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:27	RWL	RO	ROMSIP	MMIOCFG SN13 base This 5 bits are sub node13 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N13_BASE[27:23]		vcc	x	x	x
26:22	RWL	RO	ROMSIP	MMIOCFG SN14 base This 5 bits are sub node14 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N14_BASE[27:23]		vcc	x	x	x
21:17	RWL	RO	ROMSIP	MMIOCFG SN15 base This 5 bits are sub node15 MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA=CP1RD[63:62])) ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N15_BASE[27:23]		vcc	x	x	x
16:14	RWL	RO	0	MMIO Below 2G (MMIOB2G) base address MMIOB2G base address, A[39:32] are fixed to 0, A[31] is fixed to 0, A[30:28] are programmable, A[27:0] are fixed to 0. MMIOB2G Limit address is fixed to 2G-1, when MMIOB2G is valid, any address X hit MMIOB2G range( MMIOB2G_base <= X <=MMIOB2G_Limit) is claimed by MMIO decoder. ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock=lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GBASE[30:28]		vcc	x	x	x
13:10	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry0 target node A[30:26]==5’d0: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ0[3:0]		vcc	x	x	x
9:6	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry1 target node A[30:26]==5’d1: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ1[3:0]		vcc	x	x	x
5:2	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry2 target node A[30:26]==5’d2: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ2[3:0]		vcc	x	x	x
1:0	RO	NA	0	Reserved	Rx9C[1:0]		vcc	x	x	x

Offset Address: A3-A0h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry3 target node A[30:26]==5’d3: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ3[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry4 target node A[30:26]==5’d4: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ4[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry5 target node A[30:26]==5’d5: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry6 target node A[30:26]==5’d6: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ6[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry7 target node A[30:26]==5’d7: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ7[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry8 target node A[30:26]==5’d8: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ8[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry9 target node A[30:26]==5’d9: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry10 target node A[30:26]==5’d10: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ10[3:0]		vcc	x	x	x

Offset Address: A7-A4h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry11 target node A[30:26]==5’d11: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ11[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry12 target node A[30:26]==5’d12: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ12[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry13 target node A[30:26]==5’d13: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry14 target node A[30:26]==5’d14: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ14[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry15 target node A[30:26]==5’d15: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ15[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry16 target node A[30:26]==5’d16: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ16[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry17 target node A[30:26]==5’d17: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ17[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry18 target node A[30:26]==5’d18: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ18[3:0]		vcc	x	x	x

Offset Address: AB-A8h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry19 target node A[30:26]==5’d19: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ19[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry20 target node A[30:26]==5’d20: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ20[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry21 target node A[30:26]==5’d21: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ21[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry22 target node A[30:26]==5’d22: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ22[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry23 target node A[30:26]==5’d23: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ23[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry24 target node A[30:26]==5’d24: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ24[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry25 target node A[30:26]==5’d25: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ25[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry26 target node A[30:26]==5’d26: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ26[3:0]		vcc	x	x	x

Offset Address: AF-ACh (D0F2)
MMIOB2G and MMIO2T4G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry27 target node A[30:26]==5’d27: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ27[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry28 target node A[30:26]==5’d28: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ28[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry29 target node A[30:26]==5’d29: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ29[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry30 target node A[30:26]==5’d30: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ30[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G(MMIOB2G) entry31 target node A[30:26]==5’d31: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ31[3:0]		vcc	x	x	x
11:9	RWL	RO	0	MMIO 2 to 4G (MMIO2T4G) base address MMIO2T4G base address, A[39:32] are fixed to 0, A[31] is fixed to 1, A[30:28] are programmable, A[27:0] are fixed to 0. MMIO2T4G Limit address is fixed to 4G-1, any address X hit MMIO2T4G range( MMIO2T4G_base <= X <=MMIO2T4G_Limit) is claimed by MMIO decoder. ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock=lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GBASE[30:28]		vcc	x	x	x
8:5	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry0 target node A[30:26]==5’d0: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock=lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ0[3:0]		vcc	x	x	x
4:1	RWL	RO	0	MMIO 2 to 4G (MMIO2T4G) entry1 target node A[30:26]==5’d1: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock=lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4G TMVEQ1[3:0]		vcc	x	x	x
0	RO	NA	0	Reserved	RxAC[0]		vcc	x	x	x

Offset Address: B3-B0h (D0F2)
MMIO2T4G decoder Default Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry2 target node A[30:26]==5’d2: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ2[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry3 target node A[30:26]==5’d3: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ3[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry4 target node A[30:26]==5’d4: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ4[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry5 target node A[30:26]==5’d5: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ5[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry6 target node A[30:26]==5’d6: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ6[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry7 target node A[30:26]==5’d7: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ7[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry8 target node A[30:26]==5’d8: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ8[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry9 target node A[30:26]==5’d9: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ9[3:0]		vcc	x	x	x

Offset Address: B7-B4h (D0F2)
MMIO2T4G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry10 target node A[30:26]==5’d10: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ10[3:0]		Vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry11 target node A[30:26]==5’d11: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ11[3:0]		Vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry12 target node A[30:26]==5’d12: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ12[3:0]		Vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry13 target node A[30:26]==5’d13: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ13[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry14 target node A[30:26]==5’d14: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ14[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry15 target node A[30:26]==5’d15: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ15[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry16 target node A[30:26]==5’d16: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ16[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry17 target node A[30:26]==5’d17: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ17[3:0]		vcc	x	x	x

Offset Address: BB-B8h (D0F2)
MMIO2T4G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry18 target node A[30:26]==5’d18: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ18[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry19 target node A[30:26]==5’d19: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ19[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry20 target node A[30:26]==5’d20: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ20[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry21 target node A[30:26]==5’d21: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ21[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry22 target node A[30:26]==5’d22: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ22[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry23 target node A[30:26]==5’d23: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ23[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry24 target node A[30:26]==5’d24: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ24[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry25 target node A[30:26]==5’d25: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ25[3:0]		vcc	x	x	x

Offset Address: BF-BCh (D0F2)
MMIO2T4G and VGA ABSEG decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry26 target node A[30:26]==5’d26: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ26[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry27 target node A[30:26]==5’d27: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ27[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry28 target node A[30:26]==5’d28: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ28[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry29 target node A[30:26]==5’d29: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ29[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry30 target node A[30:26]==5’d30: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ30[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 to 4G(MMIO2T4G) entry31 target node A[30:26]==5’d31: the request is routed to the node indicated by this register value	RSVAD_MMIO2T4GTMVEQ31[3:0]		vcc	x	x	x
7	RWL	NA	0	C2M Tseg range Protection control When this bit set to 1 then C2M Tseg range protection is removed. This bit is valid only when Rx9C[2,1] = [0,0], please reference table 1 for detail. Note: The DMA protection is always enabled, do not effect by this bit. 1: disable C2M Tseg range protection 0: enable C2M Tseg range protection Please reference table 1 ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_TSEGPRTDIS		vcc	x	x	x
6:3	RWL	RO	0	A/B SEG(VGA memory) decode for target to MMIO - for memory address range in A0000h to BFFFFh ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ABSEG_MMIO_TGT		vcc	x	x	x
2:1	RWL	RO	0	A/B & T SEG access control to system memory or MMIO Reference table1 ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ABSEG_SEL		vcc	x	x	x
0	RO	NA	0	Reserved	RxBC[0]		vcc	x	x	x

table1

Rx6C[2]	Rx6C[1]	Rx6C[7]	Cycle Type	Code Read Target	Data Access Target
0	0	0	Normal	MMIO *1	MMIO *1
0	0	0	SMM	System Memory *2	System Memory *2
0	0	1	Normal	A/B Seg ->MMIO 1 T Seg -> System Memory 3	A/B Seg ->MMIO 1 T Seg -> System Memory 3
0	0	1	SMM	System Memory *2	System Memory *2
-	1	x	Normal/SMM	System Memory *2	System Memory *2
1	0	x	Normal	MMIO *1	MMIO *1
1	0	x	SMM	System Memory *2	MMIO *1

Chipset base on the request from CPU is in normal/SMM mode and Rx6C[2:1] to re-direct the cycle to MMIO or System memory.
Note 1: For target to MMIO and in A/B SEG range, chipset also reference Rx6C[6:3] to re-direct the cycle to sub node. In Tseg range, chipset always forward the cycle to local sub node.
Note 2: For target to System Memory, chipset also reference SVAD entries to re-direct the cycle to master/slave socket.
Note 3: For target to System Memory in T seg range, it is used for CPU SMRR enable with WB cache mode only.
DMA protection:
Note 1: Chipset always protect A0000h~FFFFFh range. The DMA cycle issue by PCI or PCIE device target to this range then will be abored by Chipset: for write, discard the request and data; for read: give back all ‘1” data to device.
Note 2. When RTSMMEN = 1 then chipset protect the DMA cycle target to T SEG range.
- T SEG range start from “RLOWTOPA – T SEG size(in SM_SIZE[1:0])” to “RLOWTOPA – 1”
Note 3. When Memory Hole enable then chipset forward the cycle to PCI.
Note 4. When DPR enable, then chipset protect the DMA cycle target to DPR range.
Offset Address: C3-C0h (D0F2)
C/D/E/F SEGDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	C/D/E/F SEG decode control when target to MMIO controlled by RxA0[25:0] 0: then target is socket0; 1:then target is socket1; This register control all C/D/E/F segment. ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) Note: when target to system memory, chipset base on SVAD to select to target socket.	RSVAD_CDEFSEG_MMIO_TGT		vcc	x	x	x
27:26	RO	NA	0	Reserved	RxC0[27:26]		vcc	x	x	x
25:24	RWL	RO	0	F0000-FFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENFF[1:0]		vcc	x	x	x
23:22	RWL	RO	0	E0000-E3FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENE0[1:0]		vcc	x	x	x
21:20	RWL	RO	0	E4000-E7FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENE4[1:0]		vcc	x	x	x
19:18	RWL	RO	0	E8000-EBFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENE8[1:0]		vcc	x	x	x
17:16	RWL	RO	0	EC000-EFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENEC[1:0]		vcc	x	x	x
15:14	RWL	RO	0	D0000-D3FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SEND0[1:0]		vcc	x	x	x
13:12	RWL	RO	0	D4000-D7FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SEND4[1:0]		vcc	x	x	x
11:10	RWL	RO	0	D8000-DBFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SEND8[1:0]		vcc	x	x	x
9:8	RWL	RO	0	DC000-DFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENDC[1:0]		vcc	x	x	x
7:6	RWL	RO	0	C0000-C3FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENC0[1:0]		vcc	x	x	x
5:4	RWL	RO	0	C4000-C7FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENC4[1:0]		vcc	x	x	x
3:2	RWL	RO	0	C8000-CBFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENC8[1:0]		vcc	x	x	x
1:0	RWL	RO	0	CC000-CFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SENCC[1:0]		vcc	x	x	x

Offset Address: C7-C4h (D0F2)
MMIO decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:30	RWL	RO	0	Memory Hole 00: None 01: 512K ~ 640K 10: 15M ~ 16M (1M) 11: 14M ~ 16M (2M) Limitation: always forward to master socket MMIO space(PCI) when hit memory hole range. ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RHOLE[1:0]		vcc	x	x	x
29	RO	NA	0	Top SM Memory Enable This bit is the enable bit for the SM Memory at the top of the memory below 4G to be activated. When this bit is enabled, the memory with size defined by bits [1:0] will be deducted from the top of the system memory and be used for SM mode. Top SM Memory range : B4GMemLimit(RLOWTOPA)+1 - SM_SIZE <= X <= B4GMemLimit 0: Disabled.1: Enabled. ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	RTSMMEN		vcc	x	x	x
28:27	RWL	RO	0	Top SM Memory Size For SM mode, these two bits defined the size of the memory at the top of the memory below 4G. They are activated only when bit-2 is 1. 00: 4M. 01: 8M. 10: 16M. 11: 32M. ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	SM_SIZE[1:0]		vcc	x	x	x
26:23	RWL	RO	0	Legacy VGA IO target select – in IO range 3B0h-3BBh, 3C0h-3DFh ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_VGA_TGT[3:0]		vcc	x	x	x
22	RWL	RO	0	This bit indicate VPI link ready, BIOS will set this bit when VPI linked up and master/slave socket initial done. 1 means VPI link ready 0 means VPI not ready ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	RSVAD_DUAL_SOCKET_ACTIVE_CTL		vcc	x	x	x
21:0	RO	NA	0	Reserved	RxC4[21:0]		vcc	x	x	x

Offset Address: CB-C8h (D0F2)
MEM_ENT0Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry0 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry0 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry0 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry0 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry0 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry0 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry0 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry0 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address: CF-CCh (D0F2)
MEM_ENT0Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry0 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry0 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry0 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry0 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry0 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry0 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry0 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry0 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address: D3-D0h (D0F2)
MEM_ENT0Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry0 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry0 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0LADDR[45:28]		vcc	x	x	x
12:11				MEM entry0 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	RxD0[11:0]		vcc	x	x	x

Note1: The SVAD entry 0 base address = 0, SVAD entry 0 Limit address must not 0.
Note 2: For SVAD entry 1 to 19, the SVAD entry N base address = SVAD entry N-1 Limit address +1; This SVAD entry is invalid if SVAD entry N Limit address = SVAD entry N-1 Limit address.
programming rule: Software should update Limit address from entry 19 to 0 to avoid some corner case cause decode fail.
Offset Address: D7-D4h (D0F2)
MEM_ENT1Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry1 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry1 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry1 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry1 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry1 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry1 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry1 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry1 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address: DB-D8h (D0F2)
MEM_ENT1Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry1 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry1 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry1 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry1 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry1 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry1 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry1 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry1 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address: DF-DCh (D0F2)
MEM_ENT1Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry1 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry1 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1LADDR[45:28]		vcc	x	x	x
12:11				MEM entry1 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	RxDC[10:0]		vcc	x	x	x

Offset Address: E3-E0h (D0F2)
MEM_ENT2Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry2 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry2 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry2 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry2 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry2 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry2 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry2 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry2 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:E7-E4h (D0F2)
MEM_ENT2Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry2 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry2 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry2 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry2 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry2 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry2 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry2 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry2 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:EB-E8h (D0F2)
MEM_ENT2Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry2 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry2 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2LADDR[45:28]		vcc	x	x	x
12:11				MEM entry2 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	RxE8[10:0]		vcc	x	x	x

Offset Address: EF-ECh (D0F2)
MEM_ENT3Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry3 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry3 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry3 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry3 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry3 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry3 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry3 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry3 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:F3-F0h (D0F2)
MEM_ENT3Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry3 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry3 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry3 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry3 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry3 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry3 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry3 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry3 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:F7-F4h (D0F2)
MEM_ENT3Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry3 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry3 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3LADDR[45:28]		vcc	x	x	x
12:11				MEM entry3 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	RxF4[10:0]		vcc	x	x	x

Offset Address: FB-F8h (D0F2)
MEM_ENT4Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry4 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry4 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry4 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry4 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry4 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry4 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry4 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry4 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:FF-FCh (D0F2)
MEM_ENT4Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry4 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry4 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry4 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry4 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry4 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry4 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry4 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry4 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address: 100-10Fh (D0F0) – Reserved
Offset Address:113-110h (D0F2)
MEM_ENT4Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry4 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry4 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4LADDR[45:28]		vcc	x	x	x
12:11				MEM entry4 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx110[10:0]		vcc	x	x	x

Offset Address: 117-114h (D0F2)
MEM_ENT5Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry5 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry5 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry5 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry5 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry5 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry5 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry5 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry5 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:11B-118h (D0F2)
MEM_ENT5Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry5 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry5 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry5 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry5 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry5 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry5 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry5 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry5 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:11F-11Ch (D0F2)
MEM_ENT5Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry5 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry5 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5LADDR[45:28]		vcc	x	x	x
12:11				MEM entry5 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx11C[10:0]		vcc	x	x	x

Offset Address: 123-120h (D0F2)
MEM_ENT6Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry6 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry6 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry6 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry6 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry6 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry6 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry6 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry6 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:127-124h (D0F2)
MEM_ENT6Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry6 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry6 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry6 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry6 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry6 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry6 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry6 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry6 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:12B-128h (D0F2)
MEM_ENT6Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry6 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry6 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6LADDR[45:28]		vcc	x	x	x
12:11				MEM entry6 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx128[10:0]		vcc	x	x	x

Offset Address: 12F-12Ch (D0F2)
MEM_ENT7Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry7 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry7 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry7 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry7 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry7 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry7 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry7 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry7 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:133-130h (D0F2)
MEM_ENT7Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry7 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry7 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry7 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry7 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry7 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry7 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry7 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry7 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:137-134h (D0F2)
MEM_ENT7Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry7 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry7 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7LADDR[45:28]		vcc	x	x	x
12:11				MEM entry7 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx134[10:0]		vcc	x	x	x

Offset Address: 13b-138h (D0F2)
MEM_ENT8Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry8 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry8 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry8 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry8 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry8 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry8 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry8 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry8 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:13F-13Ch (D0F2)
MEM_ENT8Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry8 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry8 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry8 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry8 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry8 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry8 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry8 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry8 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:143-140h (D0F2)
MEM_ENT8Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry8 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry8 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8LADDR[45:28]		vcc	x	x	x
12:11				MEM entry8 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx140[10:0]		vcc	x	x	x

Offset Address: 147-144h (D0F2)
MEM_ENT9Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry9 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry9 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry9 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry9 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry9 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry9 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry9 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry9 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:14B-148h (D0F2)
MEM_ENT9Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry9 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry9 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry9 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry9 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry9 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry9 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry9 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry9 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:14F-14Ch (D0F2)
MEM_ENT9Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry9 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry9 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9LADDR[45:28]		vcc	x	x	x
12:11				MEM entry9 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx14C[10:0]		vcc	x	x	x

Offset Address: 153-150h (D0F2)
MEM_ENT10Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry10 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry10 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry10 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry10 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry10 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry10 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry10 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry10 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:157-154h (D0F2)
MEM_ENT10Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry10 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry10 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry10 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry10 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry10 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry10 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry10 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry10 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:15B-158h (D0F2)
MEM_ENT10Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry10 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry10 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10LADDR[45:28]		vcc	x	x	x
12:11				MEM entry10 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx158[10:0]		vcc	x	x	x

Offset Address: 15F-15Ch (D0F2)
MEM_ENT11Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry11 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry11 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry11 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry11 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry11 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry11 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry11 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry11 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:163-160h (D0F2)
MEM_ENT11Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry11 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry11 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry11 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry11 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry11 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry11 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry11 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry11 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:167-164h (D0F2)
MEM_ENT11Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry11 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry11 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11LADDR[45:28]		vcc	x	x	x
12:11				MEM entry11 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx164[10:0]		vcc	x	x	x

Offset Address: 16B-168h (D0F2)
MEM_ENT12Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry12 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry12 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry12 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry12 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry12 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry12 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry12 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry12 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:16F-16Ch (D0F2)
MEM_ENT12Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry12 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry12 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry12 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry12 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry12 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry12 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry12 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry12 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:173-170h (D0F2)
MEM_ENT12Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry12 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry12 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12LADDR[45:28]		vcc	x	x	x
12:11				MEM entry12 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx170[10:0]		vcc	x	x	x

Offset Address: 177-174h (D0F2)
MEM_ENT13Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry13 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry13 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry13 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry13 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry13 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry13 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry13 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry13 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:17B-178h (D0F2)
MEM_ENT13Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry13 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry13 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry13 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry13 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry13 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry13 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry13 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry13 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:17F-17Ch (D0F2)
MEM_ENT13Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry13 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry13 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13LADDR[45:28]		vcc	x	x	x
12:11				MEM entry13 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx17C[10:0]		vcc	x	x	x

Offset Address: 183-180h (D0F2)
MEM_ENT14Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry14 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry14 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry14 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry14 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry14 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry14 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry14 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry14 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:187-184h (D0F2)
MEM_ENT14Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry14 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry14 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry14 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry14 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry14 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry14 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry14 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry14 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:18B-188h (D0F2)
MEM_ENT14Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry14 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry14 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14LADDR[45:28]		vcc	x	x	x
12:11				MEM entry14 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx188[10:0]		vcc	x	x	x

Offset Address: 18F-18Ch (D0F2)
MEM_ENT15Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry15 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry15 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry15 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry15 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry15 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry15 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry15 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry15 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:193-190h (D0F2)
MEM_ENT15Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry15 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry15 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry15 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry15 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry15 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry15 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry15 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry15 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:197-194h (D0F2)
MEM_ENT15Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry15 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry15 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15LADDR[45:28]		vcc	x	x	x
12:11				MEM entry15 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx194[10:0]		vcc	x	x	x

Offset Address: 19B-198h (D0F2)
MEM_ENT16Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry16 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry16 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry16 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry16 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry16 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry16 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry16 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry16 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:19F-19Ch (D0F2)
MEM_ENT16Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry16 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry16 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry16 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry16 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry16 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry16 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry16 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry16 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1A3-1A0h (D0F2)
MEM_ENT16Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry16 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry16 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16LADDR[45:28]		vcc	x	x	x
12:11				MEM entry16 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1A0[10:0]		vcc	x	x	x

Offset Address: 1A7-1A4h (D0F2)
MEM_ENT17Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry17 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry17 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry17 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry17 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry17 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry17 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry17 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry17 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1AB-1A8h (D0F2)
MEM_ENT17Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry17 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry17 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry17 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry17 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry17 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry17 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry17 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry17 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1AF-1ACh (D0F2)
MEM_ENT17Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry17 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry17 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17LADDR[45:28]		vcc	x	x	x
12:11				MEM entry17 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1AC[10:0]		vcc	x	x	x

Offset Address: 1B3-1B0h (D0F2)
MEM_ENT18Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry18 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry18 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry18 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry18 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry18 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry18 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry18 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry18 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1B7-1B4h (D0F2)
MEM_ENT18Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry18 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry18 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry18 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry18 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry18 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry18 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry18 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry18 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1BB-1B8h (D0F2)
MEM_ENT18Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry18 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry18 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18LADDR[45:28]		vcc	x	x	x
12:11				MEM entry18 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1B8[10:0]		vcc	x	x	x

Offset Address: 1BF-1BCh (D0F2)
MEM_ENT19Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry19 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry19 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry19 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry19 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry19 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry19 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry19 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry19 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1C3-1C0h (D0F2)
MEM_ENT19Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry19 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry19 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry19 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry19 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry19 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry19 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry19 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry19 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1C7-1C4h (D0F2)
MEM_ENT19Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry19 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry19 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19LADDR[45:28]		vcc	x	x	x
12:11				MEM entry19 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1C4[10:0]		vcc	x	x	x

Offset Address: 1CB-1C8h (D0F2)
MEM_ENT20Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry20 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry20 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry20 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry20 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry20 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry20 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry20 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry20 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1CF-1CCh (D0F2)
MEM_ENT20Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry20 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry20 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry20 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry20 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry20 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry20 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry20 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry20 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1D3-1D0h (D0F2)
MEM_ENT20Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry20 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry20 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20LADDR[45:28]		vcc	x	x	x
12:11				MEM entry20 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1D0[10:0]		vcc	x	x	x

Offset Address: 1D7-1D4h (D0F2)
MEM_ENT21Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry21 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry21 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry21 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry21 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry21 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry21 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry21 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry21 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1DB-1D8h (D0F2)
MEM_ENT21Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry21 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry21 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry21 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry21 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry21 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry21 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry21 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry21 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1DF-1DCh (D0F2)
MEM_ENT21Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry21 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry21 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21LADDR[45:28]		vcc	x	x	x
12:11				MEM entry21 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1DC[10:0]		vcc	x	x	x

Offset Address: 1E3-1E0h (D0F2)
MEM_ENT22Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry22 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry22 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry22 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry22 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry22 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry22 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry22 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry22 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1E7-1E4h (D0F2)
MEM_ENT22Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry22 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry22 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry22 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry22 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry22 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry22 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry22 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry22 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1EB-1E8h (D0F2)
MEM_ENT22Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry22 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry22 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22LADDR[45:28]		vcc	x	x	x
12:11				MEM entry22 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1E8[10:0]		vcc	x	x	x

Offset Address: 1EF-1ECh (D0F2)
MEM_ENT23Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry23 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry23 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry23 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry23 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME233TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry23 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry23 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry23 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry23 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1F3-1F0h (D0F2)
MEM_ENT23Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry23 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry23 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry23 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry23 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry23 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry23 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry23 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry23 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:1F7-1F4h (D0F2)
MEM_ENT23Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry23 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry23 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23LADDR[45:28]		vcc	x	x	x
12:11				MEM entry23 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx1F4[10:0]		vcc	x	x	x

Offset Address: 1FB-1F8h (D0F2)
MEM_ENT24Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry24 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry24 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry24 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry24 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry24 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry24 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry24 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry24 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:1FF-1FCh (D0F2)
MEM_ENT24Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry24 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry24 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry24 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry24 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry24 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry24 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry24 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry24 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:203-200h (D0F2)
MEM_ENT24Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry24 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry24 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24LADDR[45:28]		vcc	x	x	x
12:11				MEM entry24 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx200[10:0]		vcc	x	x	x

Offset Address: 207-204h (D0F2)
MEM_ENT25Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry25 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry25 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry25 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry25 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry25 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry25 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry25 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry25 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:20B-208h (D0F2)
MEM_ENT25Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry25 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry25 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry25 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry25 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry25 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry25 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry25 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry25 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:20F-20Ch (D0F2)
MEM_ENT25Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry25 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry25 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25LADDR[45:28]		vcc	x	x	x
12:11				MEM entry25 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx20C[10:0]		vcc	x	x	x

Offset Address: 213-210h (D0F2)
MEM_ENT26Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry26 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry26 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry26 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry26 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry26 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry26 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry26 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry26 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:217-214h (D0F2)
MEM_ENT26Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry26 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry26 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry26 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry26 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry26 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry26 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry26 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry26 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:21B-218h (D0F2)
MEM_ENT26Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry26 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry26 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26LADDR[45:28]		vcc	x	x	x
12:11				MEM entry26 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx218[10:0]		vcc	x	x	x

Offset Address: 21F-21Ch (D0F2)
MEM_ENT27Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry27 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry27 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry27 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry27 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry27 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry27 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry27 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry27 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:223-220h (D0F2)
MEM_ENT27Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry27 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry27 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry27 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry27 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry27 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry27 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry27 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry27 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:227-224h (D0F2)
MEM_ENT27Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry27 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry27 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27LADDR[45:28]		vcc	x	x	x
12:11				MEM entry27 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx224[10:0]		vcc	x	x	x

Offset Address: 22B-228h (D0F2)
MEM_ENT28Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry28 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry28 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry28 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry28 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry28 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry28 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry28 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry28 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:22F-22Ch (D0F2)
MEM_ENT28Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry28 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry28 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry28 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry28 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry28 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry28 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry28 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry28 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:233-230h (D0F2)
MEM_ENT28Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry28 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry28 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28LADDR[45:28]		vcc	x	x	x
12:11				MEM entry28 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx230[10:0]		vcc	x	x	x

Offset Address: 237-234h (D0F2)
MEM_ENT29Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry29 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry29 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry29 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry29 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry29 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry29 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry29 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry29 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:23B-238h (D0F2)
MEM_ENT29Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry29 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry29 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry29 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry29 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry29 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry29 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry29 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry29 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:23F-23Ch (D0F2)
MEM_ENT29Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry29 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry29 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29LADDR[45:28]		vcc	x	x	x
12:11				MEM entry29 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx23C[10:0]		vcc	x	x	x

Offset Address: 243-240h (D0F2)
MEM_ENT30Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry30 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry30 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry30 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry30 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry30 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry30 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry30 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry30 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:247-244h (D0F2)
MEM_ENT30Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry30 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry30 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry30 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry30 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry30 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry30 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry30 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry30 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:24B-248h (D0F2)
MEM_ENT30Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry30 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry30 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30LADDR[45:28]		vcc	x	x	x
12:11				MEM entry30 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx248[10:0]		vcc	x	x	x

Offset Address: 24F-24Ch (D0F2)
MEM_ENT31Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry31 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry31 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry31 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry31 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry31 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry31 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry31 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry31 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:253-250h (D0F2)
MEM_ENT31Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry31 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry31 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry31 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry31 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry31 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry31 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry31 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry31 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:257-254h (D0F2)
MEM_ENT31Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry31 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry31 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31LADDR[45:28]		vcc	x	x	x
12:11				MEM entry31 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx254[10:0]		vcc	x	x	x

Offset Address: 25B-258h (D0F2)
MEM_ENT32Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry32 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry32 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry32 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry32 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry32 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry32 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry32 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry32 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:25F-25Ch (D0F2)
MEM_ENT32Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry32 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry32 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry32 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry32 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry32 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry32 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry32 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry32 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:263-260h (D0F2)
MEM_ENT32Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry32 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry32 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32LADDR[45:28]		vcc	x	x	x
12:11				MEM entry32 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx260[10:0]		vcc	x	x	x

Offset Address: 267-264h (D0F2)
MEM_ENT33Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry33 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry33 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry33 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry33 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry33 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry33 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry33 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry33 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:26B-268h (D0F2)
MEM_ENT33Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry33 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry33 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry33 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry33 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry33 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry33 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry33 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry33 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:26F-26Ch (D0F2)
MEM_ENT33Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry33 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry33 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33LADDR[45:28]		vcc	x	x	x
12:11				MEM entry33 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx26C[10:0]		vcc	x	x	x

Offset Address: 273-270h (D0F2)
MEM_ENT34Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry34 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry34 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry34 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry34 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry34 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry34 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry34 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry34 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:277-274h (D0F2)
MEM_ENT34Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry34 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry34 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry34 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry34 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry34 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry34 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry34 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry34 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:27B-278h (D0F2)
MEM_ENT34Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry34 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry34 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34LADDR[45:28]		vcc	x	x	x
12:11				MEM entry34 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx278[10:0]		vcc	x	x	x

Offset Address: 27F-27Ch (D0F2)
MEM_ENT35Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry35 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry35 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry35 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry35 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry35 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry35 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry35 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry35 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:283-280h (D0F2)
MEM_ENT35Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry35 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry35 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry35 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry35 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry35 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry35 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry35 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry35 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:287-284h (D0F2)
MEM_ENT35Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry35 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry35 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35LADDR[45:28]		vcc	x	x	x
12:11				MEM entry35 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx284[10:0]		vcc	x	x	x

Offset Address: 28B-288h (D0F2)
MEM_ENT36Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry36 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry36 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry36 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry36 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry36 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry36 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry36 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry36 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:28F-28Ch (D0F2)
MEM_ENT36Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry36 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry36 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry36 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry36 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry36 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry36 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry36 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry36 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:293-290h (D0F2)
MEM_ENT36Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry36 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry36 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36LADDR[45:28]		vcc	x	x	x
12:11				MEM entry36 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx290[10:0]		vcc	x	x	x

Offset Address: 297-294h (D0F2)
MEM_ENT37Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry37 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry37 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry37 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry37 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry37 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry37 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry37 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry37 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:29B-298h (D0F2)
MEM_ENT37Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry37 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry37 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry37 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry37 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry37 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry37 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry37 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry37 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:29F-29Ch (D0F2)
MEM_ENT37Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry37 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry37 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37LADDR[45:28]		vcc	x	x	x
12:11				MEM entry37 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx29C[10:0]		vcc	x	x	x

Offset Address: 2A3-2A0h (D0F2)
MEM_ENT38Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry38 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry38 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry38 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry38 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry38 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry38 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry38 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry38 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2A7-2A4h (D0F2)
MEM_ENT38Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry38 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry38 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry38 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry38 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry38 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry38 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry38 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry38 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2AB-2A8h (D0F2)
MEM_ENT38Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry38 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry38 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38LADDR[45:28]		vcc	x	x	x
12:11				MEM entry38 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2A8[10:0]		vcc	x	x	x

Offset Address: 2AF-2ACh (D0F2)
MEM_ENT39Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry39 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry39 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry39 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry39 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry39 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry39 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry39 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry39 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2B3-2B0h (D0F2)
MEM_ENT39Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry39 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry39 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry39 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry39 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry39 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry39 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry39 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry39 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2B7-2B4h (D0F2)
MEM_ENT39Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry39 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry39 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39LADDR[45:28]		vcc	x	x	x
12:11				MEM entry39 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2B4[10:0]		vcc	x	x	x

Offset Address: 2BB-2B8h (D0F2)
MEM_ENT40Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry40 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry40 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry40 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry40 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry40 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry40 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry40 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry40 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2BF-2BCh (D0F2)
MEM_ENT40Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry40 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry40 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry40 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry40 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry40 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry40 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry40 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry40 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2C3-2C0h (D0F2)
MEM_ENT40Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry40 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry40 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40LADDR[45:28]		vcc	x	x	x
12:11				MEM entry40 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2C0[10:0]		vcc	x	x	x

Offset Address: 2C7-2C4h (D0F2)
MEM_ENT41Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry41 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry41 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry41 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry41 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry41 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry41 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry41 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry41 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2CB-2C8h (D0F2)
MEM_ENT41Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry41 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry41 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry41 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry41 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry41 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry41 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry41 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry41 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2CF-2CCh (D0F2)
MEM_ENT41Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry41 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry41 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41LADDR[45:28]		vcc	x	x	x
12:11				MEM entry41 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2CC[10:0]		vcc	x	x	x

Offset Address: 2D3-2D0h (D0F2)
MEM_ENT42Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry42 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry42 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry42 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry42 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry42 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry42 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry42 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry42 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2D7-2D4h (D0F2)
MEM_ENT42Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry42 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry42 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry42 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry42 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry42 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry42 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry42 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry42 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2DB-2D8h (D0F2)
MEM_ENT42Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry42 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry42 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42LADDR[45:28]		vcc	x	x	x
12:11				MEM entry42 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2D8[10:0]		vcc	x	x	x

Offset Address: 2DF-2DCh (D0F2)
MEM_ENT43Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry43 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry43 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry43 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry43 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry43 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry43 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry43 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry43 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2E3-2E0h (D0F2)
MEM_ENT43Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry43 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry43 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry43 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry43 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry43 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry43 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry43 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry43 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2E7-2E4h (D0F2)
MEM_ENT43Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry43 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry43 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43LADDR[45:28]		vcc	x	x	x
12:11				MEM entry43 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2E4[10:0]		vcc	x	x	x

Offset Address: 2EB-2E8h (D0F2)
MEM_ENT44Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry44 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry44 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry44 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry44 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry44 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry44 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry44 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry44 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2EF-2ECh (D0F2)
MEM_ENT44Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry44 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry44 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry44 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry44 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry44 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry44 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry44 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry44 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2F3-2F0h (D0F2)
MEM_ENT44Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry44 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry44 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44LADDR[45:28]		vcc	x	x	x
12:11				MEM entry44 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2F0[10:0]		vcc	x	x	x

Offset Address: 2F7-2F4h (D0F2)
MEM_ENT45Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry45 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry45 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry45 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry45 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry45 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry45 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry45 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry45 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:2FB-2F8h (D0F2)
MEM_ENT45Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry45 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry45 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry45 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry45 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry45 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry45 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry45 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry45 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:2FF-2FCh (D0F2)
MEM_ENT45Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry45 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry45 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45LADDR[45:28]		vcc	x	x	x
12:11				MEM entry45 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx2FC[10:0]		vcc	x	x	x

Offset Address: 303-300h (D0F2)
MEM_ENT46Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry46 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry46 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry46 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry46 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry46 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry46 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry46 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry46 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:307-304h (D0F2)
MEM_ENT46Default Value: 00000000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry46 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry46 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry46 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry46 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry46 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry46 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry46 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry46 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:30B-308h (D0F2)
MEM_ENT46Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry46 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry46 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46LADDR[45:28]		vcc	x	x	x
12:11				MEM entry46 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx308[10:0]		vcc	x	x	x

Offset Address: 30F-30Ch (D0F2)
MEM_ENT47Default Value: 00000000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry47 TARGETLIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST0[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry47 TARGETLIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST1[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry47 TARGETLIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST2[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry47 TARGETLIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET _LIST3[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry47 TARGETLIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST4[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry47 TARGETLIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST5[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry47 TARGETLIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST6[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry47 TARGETLIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST7[3:0]		vcc	R	x	x

Offset Address:313-310h (D0F2)
MEM_ENT47Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RO	NA	0	MEM entry47 TARGETLIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET _LIST8[3:0]		vcc	R	x	x
27:24	RO	NA	0	MEM entry47 TARGETLIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST9[3:0]		vcc	R	x	x
23:20	RO	NA	0	MEM entry47 TARGETLIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST10[3:0]		vcc	R	x	x
19:16	RO	NA	0	MEM entry47 TARGETLIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST11[3:0]		vcc	R	x	x
15:12	RO	NA	0	MEM entry47 TARGETLIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST12[3:0]		vcc	R	x	x
11:8	RO	NA	0	MEM entry47 TARGETLIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST13[3:0]		vcc	R	x	x
7:4	RO	NA	0	MEM entry47 TARGETLIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST14[3:0]		vcc	R	x	x
3:0	RO	NA	0	MEM entry47 TARGETLIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST15[3:0]		vcc	R	x	x

Offset Address:317-314h (D0F2)
MEM_ENT47Default Value: 01FFE000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry47 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47ATTR		vcc	x	x	x
30:13	RWL	RO	FFFh	MEM entry47 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47LADDR[45:28]		vcc	x	x	x
12:11				MEM entry47 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47ADDR_SEL_11_9		vcc
10:0	RO	NA	0	Reserved	Rx314[10:0]		vcc	x	x	x

Offset Address: 31B-318h (D0F2)
Highest SVAD limit target to memory (DRAM limit address over 4G)Default Value: 0003FFC0h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:6	RWL	RO	FFFh	TOP of System memory address over 4G these bits defined the TOP address space over 4G that the system can use as the system memory. The address X of “4G<=X<RTOPA” is the DRAM address. BIOS should set RTOPA = 1000h if no system memory above 4G address This register is used for traffic controller to decode target of the upstream cycle to memory or MMIO(PCI) for P2P ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	RTOPA[45:20]		vcc	x	x	x
5:0	RO	NA	0	Reserved	Rx318[3:0]		vcc	x	x	x

Offset Address: 31D-31Ch (D0F2)
Below 4G highest memory limit(DRAM limit address below 4G)Default Value: FF00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:4	RWL	RO	FF0h	TOP of System memory address below 4G these bits defined the TOP address space below 4G that the system can use as the system memory. Note: BIOS MUST set Below 4G MMIO Base address = RLOWTOPA = min value of {MMIOB2G, MMIO2T4G} The address X of “X < RLOWTOPA”is the DRAM address. HW use the RLOWTOPA to decode the P2C cycle target to DRAM or MMIO. ((For Internal Reference: This bit is RW when D0F2 Rx40 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	RLOWTOPA[31:20]		vcc	x	x	x
3:0	RO	NA	0	Reserved	Rx31C[3:0]		vcc	x	x	x

Offset Address: 31F-31Eh (D0F2)
ReservedDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RO	NA	0	Reserved	Rx31E[15:0]		vcc	x	x	x

SVADLimit = highest SVAD limit address

SVAD limit address = N * 256M - 1
MemLimit +1 = highest SVAD limit target to memory(RTOPA)
MemLimit +1 = N * 256M
B4GMemLimit +1 = Below 4G highest memory limit(RLOWTOPA)
B4GMemLimit +1 = N * 256M

B4GMMIOBase = min(MMIOB2G,MMIO2T4G)

MMIOB2G Decode (90-B7h)

Offset Address: 93-90h (D0F2)
MMIOCFG decoderDefault Value: 0nnn nn00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	RDID_RID_LOCK_D0F2 ((For Internal Reference: DID_RID_lock_bit 0: DeviceID, RevisionID and RDID_RID_LOCK_D0F2 is RW; 1: DeviceID, RevisionID and RDID_RID_LOCK_D0F2 is RO; @((#control_lock = lock_port RDID_RID_LOCK_D0F2)) ))	RDID_RID_LOCK_D0F2		vcc	0	x	x
30	RWL	RO	0	RSVAD_LOCK This is a lock bit for the related register “SVAD”: 1: When this ((Lock_bit)) is set to 1, the SVAD related register is RO. 0: When this ((Lock_bit)) is set to 0, the SVAD related regisrer is RW ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) @((#control_txt_lock = LOCK_SMRAM)) @((#control_txt_unlock = UNLOCK_SMRAM)) )) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_LOCK		vcc	x	x	x
29	RWL	RO	0	RVID_DID_LOCK_D0F2 ((For Internal Reference: VID_DID_lock_bit 0: VendorID and RVID_DID_LOCK_D0F2 is RW; 1: VendorID and RVID_DID_LOCK_D0F2 is RO; @((#control_lock = lock_port RVID_DID_LOCK_D0F2)) @((#control_default = NB_VID_DID_LOCK)) ))	RVID_DID_LOCK_D0F2		vcc	x	x	x
28	RWL	RO	0	C2M_Tseg_range _LOCK_D0F2 0: C2M Tseg range control is RW; 1: C2M Tseg range Protection control is RO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0. @((#control_lock=lock_port RSVAD_TSEGLOCK )) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_TSEGLOCK		vcc	x	x	x
27:8	RWL	RO	ROMSIP	MMIOCFG base This 20 bits are MMIOCFG base address ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[59:40])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFGBASE[45:26]		vcc	x	x	x
7:3	RO	NA	0	Reserved	Rx90[7:3]		vcc	R	x	x
2	RWL	RO	0	RCLASS_CODE_LOCK_D0F2 ((For Internal Reference: ClassCode_lock_bit 0: ClassCode and RCLASS_CODE_LOCK_D0F2 is RW; 1: ClassCode and RCLASS_CODE_LOCK_D0F2 is RO; @((#control_lock = lock_port RCLASS_CODE_LOCK_D0F2)) ))	RCLASS_CODE_LOCK_D0F2		vcc	x	x	x
1	RWL	RO	0	C2M_CDEFseg_range_LOCK_D0F2 0: C2M CDEFGseg range control is RW; 1: C2M CDEFseg range Protection control is RO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock=lock_port RSVAD_CDEFSEGLOCK )) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_CDEFSEGLOCK		vcc	x	x	x
0	RO	NA	0	Reserved	Rx90[0]		vcc	R	x	x

Offset Address: 97-94h (D0F2)
MMIOCFG limit addressDefault Value:nnnn nnnnh

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:29	RO	NA	0	Reserved	Rx94[31:29]		vcc	R	x	x
28:24	RWL	RO	ROMSIP	MMIOCFG SN3 bus number limit This 5 bits are sub node3 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[24:20])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N3_LIMIT [27:23]		vcc	x	x	x
23:21	RO	NA	0	Reserved	Rx94[23:21]		vcc	R	x	x
20:16	RWL	RO	ROMSIP	MMIOCFG SN2 bus number limit This 5 bits are sub node2 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[29:25])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N2_LIMIT [27:23]		vcc	x	x	x
15:13	RO	NA	0	Reserved	Rx94[15:13]		vcc	R	x	x
12:8	RWL	RO	ROMSIP	MMIOCFG SN1 bus number limit This 5 bits are sub node1 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[34:30])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N1_LIMIT[27:23]		vcc	x	x	x
7:5	RO	NA	0	Reserved	Rx94[7:5]		vcc	R	x	x
4:0	RWL	RO	ROMSIP	MMIOCFG SN0 bus number limit This 5 bits are sub node0 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[39:35])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N0_LIMIT[27:23]		vcc	x	x	x

Offset Address: 9B-98h (D0F2)
MMIOCFG limit addressDefault Value: nnnn nnnnh

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:29	RO	NA	0	Reserved	Rx98[31:29]		vcc	R	x	x
28:24	RWL	RO	ROMSIP	MMIOCFG SN7 bus number limit This 5 bits are sub node7 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[4:0])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N7_LIMIT [27:23]		vcc	x	x	x
23:21	RO	NA	0	Reserved	Rx98[23:21]		vcc	R	x	x
20:16	RWL	RO	ROMSIP	MMIOCFG SN6 bus number limit This 5 bits are sub node6 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[9:5])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N6_LIMIT [27:23]		vcc	x	x	x
15:13	RO	NA	0	Reserved	Rx98[15:13]		vcc	R	x	x
12:8	RWL	RO	ROMSIP	MMIOCFG SN5 bus number limit This 5 bits are sub node5 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[14:10])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N5_LIMIT[27:23]		vcc	x	x	x
7:5	RO	NA	0	Reserved	Rx98[7:5]		vcc	R	x	x
4:0	RWL	RO	ROMSIP	MMIOCFG SN4 bus number limit This 5 bits are sub node4 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[19:15])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N4_LIMIT[27:23]		vcc	x	x	x

Offset Address: 9F-9Ch (D0F2)
MMIOCFG limit addressDefault Value: nnnn nnnnh

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:29	RO	NA	0	Reserved	Rx9C[31:29]		vcc	R	x	x
28:24	RWL	RO	ROMSIP	MMIOCFG SN11 bus number limit This 5 bits are sub node11 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[48:44])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N11_LIMIT [27:23]		vcc	x	x	x
23:21	RO	NA	0	Reserved	Rx9C[23:21]		vcc	R	x	x
20:16	RWL	RO	ROMSIP	MMIOCFG SN10 bus number limit This 5 bits are sub node10 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[53:49])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N10_LIMIT [27:23]		vcc	x	x	x
15:13	RO	NA	0	Reserved	Rx9C[15:13]		vcc	R	x	x
12:8	RWL	RO	ROMSIP	MMIOCFG SN9 bus number limit This 5 bits are sub node9 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[58:54])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N9_LIMIT[27:23]		vcc	x	x	x
7:5	RO	NA	0	Reserved	Rx9C[7:5]		vcc	R	x	x
4:0	RWL	RO	ROMSIP	MMIOCFG SN8 bus number limit This 5 bits are sub node8 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[63:59])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N8_LIMIT[27:23]		vcc	x	x	x

Offset Address: A3-A0h (D0F2)
MMIOCFG limit addressDefault Value: nnnn nnnnh

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:29	RO	NA	0	Reserved	RxA0[31:29]		vcc	R	x	x
28:24	RWL	RO	ROMSIP	MMIOCFG SN15 bus number limit This 5 bits are sub node15 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[28:24])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N15_LIMIT [27:23]		vcc	x	x	x
23:21	RO	NA	0	Reserved	RxA0[23:21]		vcc	R	x	x
20:16	RWL	RO	ROMSIP	MMIOCFG SN14 bus number limit This 5 bits are sub node14 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[33:29])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N14_LIMIT [27:23]		vcc	x	x	x
15:13	RO	NA	0	Reserved	RxA0[15:13]		vcc	R	x	x
12:8	RWL	RO	ROMSIP	MMIOCFG SN13 bus number limit This 5 bits are sub node13 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[38:34])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N13_LIMIT[27:23]		vcc	x	x	x
7:5	RO	NA	0	Reserved	RxA0[7:5]		vcc	R	x	x
4:0	RWL	RO	ROMSIP	MMIOCFG SN12 bus number limit This 5 bits are sub node12 MMIOCFG bus number limit. ((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[43:39])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOCFG_N12_LIMIT[27:23]		vcc	x	x	x

Offset Address: A7-A4h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:4	RO	NA	0	Reserved	RxA4[31:4]		vcc	R	x	x
3:1	RWL	RO	0	MMIO Below 2G (MMIOB2G) base address MMIOB2G base address, A[39:32] are fixed to 0, A[31] is fixed to 0, A[30:28] are programmable, A[27:0] are fixed to 0. MMIOB2G Limit address is fixed to 2G-1, when MMIOB2G is valid, any address X hit MMIOB2G range( MMIOB2G_base <= X <=MMIOB2G_Limit) is claimed by MMIO decoder. ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock=lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GBASE[30:28]		vcc	x	x	x
0	RWL	RO	0	MMIO Below 2G disable 1: MMIO Below 2G is invalid 0: MMIO Below 2G is valid ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2G_DIS		vcc	x	x	x

Offset Address: AB-A8h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry7 target node A[30:26]==5’d7: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry6 target node A[30:26]==5’d6: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry5 target node A[30:26]==5’d5: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry4 target node A[30:26]==5’d4: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry3 target node A[30:26]==5’d3: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry2 target node A[30:26]==5’d2: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry1 target node A[30:26]==5’d1: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry0 target node A[30:26]==5’d0: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ0[3:0]		vcc	x	x	x

Offset Address: AF-ACh (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry15 target node A[30:26]==5’d15: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry14 target node A[30:26]==5’d14: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry13 target node A[30:26]==5’d13: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry12 target node A[30:26]==5’d12: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry11 target node A[30:26]==5’d11: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry10 target node A[30:26]==5’d10: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry9 target node A[30:26]==5’d9: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry8 target node A[30:26]==5’d8: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ8[3:0]		vcc	x	x	x

Offset Address: B3-B0h (D0F2)
MMIOB2G decoder Default Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry23 target node A[30:26]==5’d23: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ23[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry22 target node A[30:26]==5’d22: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ22[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry21 target node A[30:26]==5’d21: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ21[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry20 target node A[30:26]==5’d20: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ20[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry19 target node A[30:26]==5’d19: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ19[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry18 target node A[30:26]==5’d18: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ18[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry17 target node A[30:26]==5’d17: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ17[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry16 target node A[30:26]==5’d16: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ16[3:0]		vcc	x	x	x

Offset Address: B7-B4h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry31 target node A[30:26]==5’d31: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ31[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry30 target node A[30:26]==5’d30: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ30[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry29 target node A[30:26]==5’d29: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ29[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry28 target node A[30:26]==5’d28: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ28[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry27 target node A[30:26]==5’d27: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ27[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry26 target node A[30:26]==5’d26: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ26[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry25 target node A[30:26]==5’d25: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ25[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO Below 2G (MMIOB2G) entry24 target node A[30:26]==5’d24: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIOB2GTMVEQ24[3:0]		vcc	x	x	x

MMIO2T4G Decode (B8-CBh)

Offset Address: BB-B8h (D0F2)
MMIO2T4G decoderDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:3	RO	NA	0	Reserved	RxB8[31:3]		vcc	x	x	x
2:0	RWL	RO	0	MMIO 2 to 4G (MMIO2T4G) base address MMIO2T4G base address, A[39:32] are fixed to 0, A[31] is fixed to 1, A[30:28] are programmable, A[27:0] are fixed to 0. MMIO2T4G Limit address is fixed to 4G-1, any address X hit MMIO2T4G range( MMIO2T4G_base <= X <=MMIO2T4G_Limit) is claimed by MMIO decoder. ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock=lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GBASE[30:28]		vcc	x	x	x

Offset Address: BF-BCh (D0F2)
MMIO2T4G decodeDefault Value:0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry7 target node A[30:26]==5’d7: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry6 target node A[30:26]==5’d6: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry5 target node A[30:26]==5’d5: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry4 target node A[30:26]==5’d4: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry3 target node A[30:26]==5’d3: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry2 target node A[30:26]==5’d2: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry1 target node A[30:26]==5’d1: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry0 target node A[30:26]==5’d0: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ0[3:0]		vcc	x	x	x

Offset Address: C3-C0h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry15 target node A[30:26]==5’d15: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry14 target node A[30:26]==5’d14: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry13 target node A[30:26]==5’d13: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry12 target node A[30:26]==5’d12: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry11 target node A[30:26]==5’d11: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry10 target node A[30:26]==5’d10: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry9 target node A[30:26]==5’d9: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry8 target node A[30:26]==5’d8: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ8[3:0]		vcc	x	x	x

Offset Address: C7-C4h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry23 target node A[30:26]==5’d23: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ23[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry22 target node A[30:26]==5’d22: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ22[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry21 target node A[30:26]==5’d21: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ21[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry20 target node A[30:26]==5’d20: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ20[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry19 target node A[30:26]==5’d19: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ19[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry18 target node A[30:26]==5’d18: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ18[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry17 target node A[30:26]==5’d17: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ17[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry16 target node A[30:26]==5’d16: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ16[3:0]		vcc	x	x	x

Offset Address: CB-C8h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry31 target node A[30:26]==5’d31: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ31[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry30 target node A[30:26]==5’d30: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ30[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry29 target node A[30:26]==5’d29: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ29[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry28 target node A[30:26]==5’d28: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ28[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry27 target node A[30:26]==5’d27: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ27[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry26 target node A[30:26]==5’d26: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ26[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry25 target node A[30:26]==5’d25: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ25[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MMIO 2 To 4G (MMIO2T4G) entry24 target node A[30:26]==5’d24: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_MMIO2T4GTMVEQ24[3:0]		vcc	x	x	x

ABSEG (CC-D3h)

Offset Address: CF-CCh (D0F2)
ABSEGDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:8	RO	NA	0	Reserved	RxC8[31:8]		vcc	R	x	x
7	RWL	NA	0	C2M Tseg range Protection control When this bit set to 1 then C2M Tseg range protection is removed. This bit is valid only when RxCC[2,1] = [0,0], please reference table 1 for detail. Note: The DMA protection is always enabled, do not effect by this bit. 1: disable C2M Tseg range protection 0: enable C2M Tseg range protection Please reference table 1 ((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0. @((#control_lock = lock_port RSVAD_TSEGLOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_TSEGPRTDIS		vcc	x	x	x
6:3	RWL	RO	0	A/B SEG(VGA memory) decode for target to MMIO - for memory address range in A0000h to BFFFFh ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ABSEG_MMIO_TGT		vcc	x	x	x
2:1	RWL	RO	0	A/B & T SEG access control to system memory or MMIO Reference table1 ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ABSEG_SEL		vcc	x	x	x
0	RO	NA	0	Reserved	RxBC[0]		vcc	R	x	x

table1

RxCC[2]	RxCC[1]	RxCC[7]	Cycle Type	Code Read Target	Data Access Target
0	0	0	Normal	MMIO *1	MMIO *1
0	0	0	SMM	System Memory *2	System Memory *2
0	0	1	Normal	A/B Seg ->MMIO 1 T Seg -> System Memory 3	A/B Seg ->MMIO 1 T Seg -> System Memory 3
0	0	1	SMM	System Memory *2	System Memory *2
-	1	x	Normal/SMM	System Memory *2	System Memory *2
1	0	x	Normal	MMIO *1	MMIO *1
1	0	x	SMM	System Memory *2	MMIO *1

Chipset base on the request from CPU is in normal/SMM mode and RxCC[2:1] to re-direct the cycle to MMIO or System memory.

Note 1: For target to MMIO and in A/B SEG range, chipset also reference RxCC[2:1] to re-direct the cycle to sub node. In Tseg range, chipset always forward the cycle to local sub node.

Note 2: For target to System Memory, chipset also reference SVAD entries to re-direct the cycle to master/slave socket.

Note 3: For target to System Memory in T seg range, it is used for CPU SMRR enable with WB cache mode only.

DMA protection:

Note 1: Chipset always protect A0000h~FFFFFh range. The DMA cycle issue by PCI or PCIE device target to this range then will be abored by Chipset: for write, discard the request and data; for read: give back all ‘1” data to device.

Note 2. When RTSMMEN = 1 then chipset protect the DMA cycle target to T SEG range.

- T SEG range start from “RLOWTOPA – T SEG size(in SM_SIZE[1:0])” to “RLOWTOPA – 1”

Note 3. When Memory Hole enable then chipset forward the cycle to PCI.

Note 4. When DPR enable, then chipset protect the DMA cycle target to DPR range.

Offset Address: D3-D0h (D0F2)
C/D/E/F SEGDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	C/D/E/F SEG decode control when target to MMIO controlled by RxD0[25:0] The value is the target sub node number; This register control all C/D/E/F segment. ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) )) Note: when target to system memory, chipset base on SVAD to select to target socket.	RSVAD_CDEFSEG_MMIO_TGT		vcc	x	x	x
27:26	RO	NA	0	Reserved	RxCC[27:26]		vcc	x	x	x
25:24	RWL	RO	0	F0000-FFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENFF[1:0]		vcc	x	x	x
23:22	RWL	RO	0	E0000-E3FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENE0[1:0]		vcc	x	x	x
21:20	RWL	RO	0	E4000-E7FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENE4[1:0]		vcc	x	x	x
19:18	RWL	RO	0	E8000-EBFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENE8[1:0]		vcc	x	x	x
17:16	RWL	RO	0	EC000-EFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENEC[1:0]		vcc	x	x	x
15:14	RWL	RO	0	D0000-D3FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SEND0[1:0]		vcc	x	x	x
13:12	RWL	RO	0	D4000-D7FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SEND4[1:0]		vcc	x	x	x
11:10	RWL	RO	0	D8000-DBFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SEND8[1:0]		vcc	x	x	x
9:8	RWL	RO	0	DC000-DFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENDC[1:0]		vcc	x	x	x
7:6	RWL	RO	0	C0000-C3FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENC0[1:0]		vcc	x	x	x
5:4	RWL	RO	0	C4000-C7FFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENC4[1:0]		vcc	x	x	x
3:2	RWL	RO	0	C8000-CBFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENC8[1:0]		vcc	x	x	x
1:0	RWL	RO	0	CC000-CFFFFh Memory Space Access Control 00b: Read / Write disable; 01b: Write enable; 10b: Read enable; 11b: Read / Write enable ((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0. @((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))	SENCC[1:0]		vcc	x	x	x

MMIO VGA IO and Legacy IO Decode (D4-10Fh)

Offset Address: D7-D4h (D0F2)
MMIO and VGA IO decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:30	RWL	RO	0	Memory Hole 00: None 01: 512K ~ 640K 10: 15M ~ 16M (1M) 11: 14M ~ 16M (2M) Limitation: always forward to master socket MMIO space(PCI) when hit memory hole range. ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RHOLE[1:0]		vcc	x	x	x
29	RWL	RO	0	Top SM Memory Enable This bit is the enable bit for the SM Memory at the top of the memory below 4G to be activated. When this bit is enabled, the memory with size defined by bits [1:0] will be deducted from the top of the system memory and be used for SM mode. Top SM Memory range : B4GMemLimit(RLOWTOPA)+1 - SM_SIZE <= X <= B4GMemLimit 0: Disabled.1: Enabled. ((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0. @((#control_lock = lock_port RSVAD_TSEGLOCK)) ))	RTSMMEN		vcc	x	x	x
28:27	RWL	RO	0	Top SM Memory Size For SM mode, these two bits defined the size of the memory at the top of the memory below 4G. They are activated only when bit-2 is 1. 00: 4M. 01: 8M. 10: 16M. 11: 32M. ((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0. @((#control_lock = lock_port RSVAD_TSEGLOCK)) ))	SM_SIZE[1:0]		vcc	x	x	x
26:5	RO	NA	0	Reserved	RxD0[26:5]		vcc	R	x	x
4:1	RWL	RO	0	Legacy VGA IO target select – in IO range 3B0h-3BBh, 3C0h-3DFh ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_VGA_TGT[3:0]		vcc	x	x	x
0	RO	NA	0	Reserved	RxD0[0]		vcc	R	x	x

Offset Address: DB-D8h (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	Legacy IO entry7 target node A[15:11]==5’d7: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	Legacy IO entry6 target node A[15:11]==5’d6: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	Legacy IO entry5 target node A[15:11]==5’d5: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	Legacy IO entry4 target node A[15:11]==5’d4: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	Legacy IO entry3 target node A[15:11]==5’d3: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	Legacy IO entry2 target node A[15:11]==5’d2: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	Legacy IO entry1 target node A[15:11]==5’d1: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	Legacy IO entry0 target node A[15:11]==5’d0: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT0[3:0]		vcc	x	x	x

Offset Address: DF-DCh (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	Legacy IO entry15 target node A[15:11]==5’d7: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	Legacy IO entry14 target node A[15:11]==5’d14: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	Legacy IO entry13 target node A[15:11]==5’d13: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	Legacy IO entry12 target node A[15:11]==5’d12: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	Legacy IO entry11 target node A[15:11]==5’d11: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	Legacy IO entry10 target node A[15:11]==5’d10: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	Legacy IO entry9 target node A[15:11]==5’d9: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	Legacy IO entry8 target node A[15:11]==5’d8: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT8[3:0]		vcc	x	x	x

Offset Address: E3-E0h (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	Legacy IO entry23 target node A[15:11]==5’d23: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT23[3:0]		vcc	x	x	x
27:24	RWL	RO	0	Legacy IO entry22 target node A[15:11]==5’d22: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT22[3:0]		vcc	x	x	x
23:20	RWL	RO	0	Legacy IO entry21 target node A[15:11]==5’d21: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT21[3:0]		vcc	x	x	x
19:16	RWL	RO	0	Legacy IO entry20 target node A[15:11]==5’d20: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT20[3:0]		vcc	x	x	x
15:12	RWL	RO	0	Legacy IO entry19 target node A[15:11]==5’d19: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT19[3:0]		vcc	x	x	x
11:8	RWL	RO	0	Legacy IO entry18 target node A[15:11]==5’d18: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT18[3:0]		vcc	x	x	x
7:4	RWL	RO	0	Legacy IO entry17 target node A[15:11]==5’d17: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT17[3:0]		vcc	x	x	x
3:0	RWL	RO	0	Legacy IO entry16 target node A[15:11]==5’d16: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT16[3:0]		vcc	x	x	x

Offset Address: E7-E4h (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	Legacy IO entry31 target node A[15:11]==5’d31: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT31[3:0]		vcc	x	x	x
27:24	RWL	RO	0	Legacy IO entry30 target node A[15:11]==5’d30: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT30[3:0]		vcc	x	x	x
23:20	RWL	RO	0	Legacy IO entry29 target node A[15:11]==5’d29: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT29[3:0]		vcc	x	x	x
19:16	RWL	RO	0	Legacy IO entry28 target node A[15:11]==5’d28: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT28[3:0]		vcc	x	x	x
15:12	RWL	RO	0	Legacy IO entry27 target node A[15:11]==5’d27: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT27[3:0]		vcc	x	x	x
11:8	RWL	RO	0	Legacy IO entry26 target node A[15:11]==5’d26: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT26[3:0]		vcc	x	x	x
7:4	RWL	RO	0	Legacy IO entry25 target node A[15:11]==5’d25: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT25[3:0]		vcc	x	x	x
3:0	RWL	RO	0	Legacy IO entry24 target node A[15:11]==5’d24: the request is routed to the node indicated by this register value ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_IO_TGT_SEL_ENT24[3:0]		vcc	x	x	x

Offset Address: E9-E8h (D0F2)
Multi-die link readyDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:1	RO	NA	0	Reserved	RxE8[15:1]		vcc	R	x	x
0	RWL	RO	0	This bit indicate all ZPI/OPI link of the platform initial done. 1 means ZPI/OPI link ready 0 means ZPI/OPI not ready ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	MULTI_DIE_ALL_LINK_READY		vcc	x	x	x

Offset Address: EA-10Fh (D0F2) – Reserved

MEM ENTRY (110-34Fh)

Offset Address: 113-110h (D0F2)
MEM_ENT0Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry0 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry0 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry0 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry0 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry0 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry0 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry0 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry0 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 117-114h (D0F2)
MEM_ENT0Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry0 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry0 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry0 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry0 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry0 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry0 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry0 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry0 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 11B-118h (D0F2)
MEM_ENT0Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry0 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry0 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry0 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME0ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx118[11:0]		vcc	x	x	x

Note1: The SVAD entry 0 base address = 0, SVAD entry 0 Limit address must not 0.

Note 2: For SVAD entry 1 to 47, the SVAD entry N base address = SVAD entry N-1 Limit address +1; This SVAD entry is invalid if SVAD entry N Limit address = SVAD entry N-1 Limit address.

programming rule: Software should update Limit address from entry 47 to 0 to avoid some corner case cause decode fail.

Offset Address: 11F-11Ch (D0F2)
MEM_ENT1Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry1 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry1 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry1 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry1 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry1 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry1 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry1 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry1 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 123-120h (D0F2)
MEM_ENT1Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry1 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry1 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry1 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry1 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry1 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry1 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry1 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry1 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 127-124h (D0F2)
MEM_ENT1Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry1 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry1 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry1 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME1ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx124[10:0]		vcc	x	x	x

Offset Address: 12B-128h (D0F2)
MEM_ENT2Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry2 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry2 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry2 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry2 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry2 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry2 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry2 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry2 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:12F-12Ch (D0F2)
MEM_ENT2Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry2 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry2 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry2 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry2 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry2 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry2 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry2 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry2 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:133-130h (D0F2)
MEM_ENT2Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry2 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry2 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry2 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME2ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx130[10:0]		vcc	x	x	x

Offset Address: 137-134h (D0F2)
MEM_ENT3Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry3 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry3 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry3 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry3 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry3 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry3 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry3 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry3 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 13B-138h (D0F2)
MEM_ENT3Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry3 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry3 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry3 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry3 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry3 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry3 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry3 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry3 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 13F-13Ch (D0F2)
MEM_ENT3Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry3 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry3 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry3 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME3ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx13C[11:0]		vcc	x	x	x

Offset Address: 143-140h (D0F2)
MEM_ENT4Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry4 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry4 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry4 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry4 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry4 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry4 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry4 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry4 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 147-144h (D0F2)
MEM_ENT4Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry4 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry4 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry4 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry4 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry4 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry4 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry4 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry4 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 14B-148h (D0F2)
MEM_ENT4Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry4 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry4 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry4 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME4ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx148[10:0]		vcc	x	x	x

Offset Address: 14F-14Ch (D0F2)
MEM_ENT5Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry5 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry5 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry5 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry5 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry5 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry5 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry5 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry5 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:153-150h (D0F2)
MEM_ENT5Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry5 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry5 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry5 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry5 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry5 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry5 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry5 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry5 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:157-154h (D0F2)
MEM_ENT5Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry5 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry5 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry5 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME5ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx154[10:0]		vcc	x	x	x

Offset Address: 15B-158h (D0F2)
MEM_ENT6Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry6 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry6 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry6 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry6 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry6 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry6 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry6 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry6 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 15F-15Ch (D0F2)
MEM_ENT6Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry6 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry6 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry6 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry6 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry6 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry6 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry6 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry6 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 163-160h (D0F2)
MEM_ENT6Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry6 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry6 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry6 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME6ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx160[11:0]		vcc	x	x	x

Offset Address: 167-164h (D0F2)
MEM_ENT7Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry7 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry7 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry7 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry7 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry7 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry7 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry7 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry7 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 16B-168h (D0F2)
MEM_ENT7Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry7 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry7 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry7 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry7 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry7 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry7 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry7 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry7 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 16F-16Ch (D0F2)
MEM_ENT7Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry7 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry7 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry7 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME7ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx16C[10:0]		vcc	x	x	x

Offset Address: 173-170h (D0F2)
MEM_ENT8Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry8 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry8 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry8 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry8 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry8 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry8 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry8 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry8 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:177-174h (D0F2)
MEM_ENT8Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry8 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry8 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry8 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry8 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry8 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry8 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry8 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry8 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:17B-178h (D0F2)
MEM_ENT8Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry8 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry8 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry8 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME8ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx178[10:0]		vcc	x	x	x

Offset Address: 17F-17Ch (D0F2)
MEM_ENT9Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry9 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry9 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry9 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry9 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry9 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry9 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry9 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry9 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 183-180h (D0F2)
MEM_ENT9Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry9 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry9 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry9 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry9 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry9 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry9 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry9 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry9 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 187-184h (D0F2)
MEM_ENT9Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry9 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry9 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry9 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME9ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx184[11:0]		vcc	x	x	x

Offset Address: 18B-188h (D0F2)
MEM_ENT10Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry10 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry10 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry10 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry10 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry10 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry10 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry10 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry10 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 18F-18Ch (D0F2)
MEM_ENT10Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry10 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry10 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry10 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry10 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry10 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry10 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry10 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry10 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 193-190h (D0F2)
MEM_ENT10Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry10 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry10 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry10 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME10ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx190[10:0]		vcc	x	x	x

Offset Address: 197-194h (D0F2)
MEM_ENT11Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry11 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry11 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry11 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry11 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry11 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry11 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry11 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry11 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:19B-198h (D0F2)
MEM_ENT11Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry11 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry11 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry11 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry11 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry11 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry11 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry11 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry11 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:19F-19Ch (D0F2)
MEM_ENT11Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry11 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry11 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry11 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME11ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx19C[10:0]		vcc	x	x	x

Offset Address: 1A3-1A0h (D0F2)
MEM_ENT12Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry12 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry12 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry12 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry12 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry12 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry12 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry12 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry12 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 1A7-1A4h (D0F2)
MEM_ENT12Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry12 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry12 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry12 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry12 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry12 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry12 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry12 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry12 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 1AB-1A8h (D0F2)
MEM_ENT12Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry12 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry12 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry12 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME12ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1A8[11:0]		vcc	x	x	x

Offset Address: 1AF-1ACh (D0F2)
MEM_ENT13Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry13 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry13 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry13 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry13 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry13 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry13 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry13 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry13 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 1B3-1B0h (D0F2)
MEM_ENT13Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry13 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry13 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry13 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry13 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry13 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry13 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry13 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry13 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13TARGET_LIST8[3:0]		vcc	x	x	x

Offset Address: 1B7-1B4h (D0F2)
MEM_ENT13Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry13 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry13 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry13 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME13ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1B4[10:0]		vcc	x	x	x

Offset Address: 1BB-1B8h (D0F2)
MEM_ENT14Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry14 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry14 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry14 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry14 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry14 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry14 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry14 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry14 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:1BF-1BCh (D0F2)
MEM_ENT14Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry14 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry14 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry14 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry14 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry14 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry14 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry14 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry14 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:1C3-1C0h (D0F2)
MEM_ENT14Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry14 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry14 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry14 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME14ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1C0[10:0]		vcc	x	x	x

Offset Address: 1C7-1C4h (D0F2)
MEM_ENT15Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry15 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry15 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry15 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry15 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry15 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry15 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry15 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry15 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 1CB-1C8h (D0F2)
MEM_ENT15Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry15 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry15 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry15 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry15 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry15 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry15 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry15 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry15 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 1CF-1CCh (D0F2)
MEM_ENT15Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry15 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry15 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry15 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME15ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1CC[11:0]		vcc	x	x	x

Offset Address: 1D3-1D0h (D0F2)
MEM_ENT16Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry16 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry16 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry16 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry16 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry16 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry16 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry16 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry16 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 1D7-1D4h (D0F2)
MEM_ENT16Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry16 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry16 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry16 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry16 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry16 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry16 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry16 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry16 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 1DB-1D8h (D0F2)
MEM_ENT16Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry16 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry16 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry16 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME16ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1D8[10:0]		vcc	x	x	x

Offset Address: 1DF-1DCh (D0F2)
MEM_ENT17Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry17 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry17 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry17 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry17 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry17 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry17 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry17 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry17 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:1E3-1E0h (D0F2)
MEM_ENT17Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry17 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry17 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry17 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry17 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry17 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry17 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry17 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry17 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:1E7-1E4h (D0F2)
MEM_ENT17Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry17 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry17 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry17 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME17ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1E4[10:0]		vcc	x	x	x

Offset Address: 1EB-1E8h (D0F2)
MEM_ENT18Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry18 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry18 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry18 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry18 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry18 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry18 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry18 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry18 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 1EF-1ECh (D0F2)
MEM_ENT18Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry18 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry18 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry18 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry18 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry18 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry18 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry18 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry18 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 1F3-1F0h (D0F2)
MEM_ENT18Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry18 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry18 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry18 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME18ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1F0[11:0]		vcc	x	x	x

Offset Address: 1F7-1F4h (D0F2)
MEM_ENT19Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry19 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry19 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry19 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry19 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry19 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry19 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry19 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry19 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 1FB-1F8h (D0F2)
MEM_ENT19Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry19 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry19 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry19 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry19 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry19 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry19 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry19 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry19 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 1FF-1FCh (D0F2)
MEM_ENT19Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry19 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry19 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry19 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME19ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx1FC[10:0]		vcc	x	x	x

Offset Address: 203-200h (D0F2)
MEM_ENT20Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry20 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry20 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry20 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry20 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry20 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry20 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry20 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry20 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:207-204h (D0F2)
MEM_ENT20Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry20 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry20 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry20 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry20 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry20 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry20 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry20 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry20 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:20B-208h (D0F2)
MEM_ENT20Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry20 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry20 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry20 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME20ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx208[10:0]		vcc	x	x	x

Offset Address: 20F-20Ch (D0F2)
MEM_ENT21Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry21 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry21 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry21 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry21 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry21 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry21 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry21 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry21 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 213-210h (D0F2)
MEM_ENT21Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry21 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry21 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry21 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry21 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry21 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry21 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry21 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry21 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 217-214h (D0F2)
MEM_ENT21Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry21 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry21 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry21 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME21ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx214[11:0]		vcc	x	x	x

Offset Address: 21B-218h (D0F2)
MEM_ENT22Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry22 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry22 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry22 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry22 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry22 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry22 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry22 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry22 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 21F-21Ch (D0F2)
MEM_ENT22Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry22 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry22 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry22 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry22 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry22 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry22 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry22 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry22 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 223-220h (D0F2)
MEM_ENT22Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry22 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry22 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry22 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME22ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx220[10:0]		vcc	x	x	x

Offset Address: 227-224h (D0F2)
MEM_ENT23Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry23 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry23 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry23 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry23 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry23 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry23 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry23 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry23 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:22B-228h (D0F2)
MEM_ENT23Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry23 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry23 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry23 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry23 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry23 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry23 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry23 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry23 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:22F-22Ch (D0F2)
MEM_ENT23Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry23 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry23 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry23 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME23ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx22C[10:0]		vcc	x	x	x

Offset Address: 233-230h (D0F2)
MEM_ENT24Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry24 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry24 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry24 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry24 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry24 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry24 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry24 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry24 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 237-234h (D0F2)
MEM_ENT24Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry24 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry24 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry24 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry24 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry24 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry24 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry24 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry24 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 23B-238h (D0F2)
MEM_ENT24Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry24 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry24 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry24 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME24ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx238[11:0]		vcc	x	x	x

Offset Address: 23F-23Ch (D0F2)
MEM_ENT25Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry1 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry1 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry1 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry1 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry1 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry1 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry1 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry1 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 243-240h (D0F2)
MEM_ENT25Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry1 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry1 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry1 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry1 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry1 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry1 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry1 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry1 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 247-244h (D0F2)
MEM_ENT25Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry1 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry1 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry1 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME25ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx244[10:0]		vcc	x	x	x

Offset Address: 24B-248h (D0F2)
MEM_ENT26Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry2 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry2 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry2 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry2 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry2 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry2 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry2 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry2 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:24F-24Ch (D0F2)
MEM_ENT26Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry2 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry2 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry2 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry2 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry2 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry2 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry2 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry2 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:253-250h (D0F2)
MEM_ENT26Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry2 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry2 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry2 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME26ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx250[10:0]		vcc	x	x	x

Offset Address: 257-254h (D0F2)
MEM_ENT27Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry27 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry27 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry27 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry27 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry27 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry27 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry27 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry27 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 25B-258h (D0F2)
MEM_ENT27Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry27 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry27 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry27 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry27 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry27 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry27 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry27 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry27 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 25F-25Ch (D0F2)
MEM_ENT27Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry27 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry27 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry27 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME27ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx25C[11:0]		vcc	x	x	x

Offset Address: 263-260h (D0F2)
MEM_ENT28Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry28 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry28 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry28 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry28 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry28 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry28 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry28 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry28 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 267-264h (D0F2)
MEM_ENT28Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry28 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry28 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry28 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry28 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry28 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry28 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry28 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry28 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 26B-268h (D0F2)
MEM_ENT28Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry28 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry28 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry28 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME28ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx268[10:0]		vcc	x	x	x

Offset Address: 26F-26Ch (D0F2)
MEM_ENT29Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry29 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry29 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry29 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry29 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry29 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry29 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry29 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry29 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:273-270h (D0F2)
MEM_ENT29Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry29 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry29 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry29 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry29 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry29 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry29 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry29 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry29 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:277-274h (D0F2)
MEM_ENT29Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry29 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry29 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry29 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME29ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx274[10:0]		vcc	x	x	x

Offset Address: 27B-278h (D0F2)
MEM_ENT30Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry30 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry30 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry30 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry30 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry30 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry30 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry30 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry30 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 27F-27Ch (D0F2)
MEM_ENT30Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry30 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry30 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry30 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry30 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry30 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry30 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry30 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry30 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 283-280h (D0F2)
MEM_ENT30Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry30 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry30 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry30 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME30ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx280[11:0]		vcc	x	x	x

Offset Address: 287-284h (D0F2)
MEM_ENT31Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry31 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry31 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry31 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry31 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry31 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry31 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry31 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry31 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 28B-288h (D0F2)
MEM_ENT31Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry31 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry31 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry31 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry31 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry31 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry31 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry31 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry31 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 28F-28Ch (D0F2)
MEM_ENT31Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry31 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry31 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry31 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME31ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx28C[10:0]		vcc	x	x	x

Offset Address: 293-290h (D0F2)
MEM_ENT32Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry32 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry32 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry32 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry32 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry32 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry32 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry32 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry32 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:297-294h (D0F2)
MEM_ENT32Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry32 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry32 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry32 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry32 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry32 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry32 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry32 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry32 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:29B-298h (D0F2)
MEM_ENT32Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry32 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry32 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry32 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME32ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx298[10:0]		vcc	x	x	x

Offset Address: 29F-29Ch (D0F2)
MEM_ENT33Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry33 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry33 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry33 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry33 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry33 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry33 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry33 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry33 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 2A3-2A0h (D0F2)
MEM_ENT33Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry33 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry33 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry33 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry33 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry33 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry33 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry33 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry33 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 2A7-2A4h (D0F2)
MEM_ENT33Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry33 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry33 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry33 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME33ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx2A4[11:0]		vcc	x	x	x

Offset Address: 2AB-2A8h (D0F2)
MEM_ENT34Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry34 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry34 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry34 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry34 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry34 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry34 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry34 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry34 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 2AF-2ACh (D0F2)
MEM_ENT34Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry34 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry34 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry34 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry34 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry34 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry34 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry34 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry34 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 2B3-2B0h (D0F2)
MEM_ENT34Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry34 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry34 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry34 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME34ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx2B0[10:0]		vcc	x	x	x

Offset Address: 2B7-2B4h (D0F2)
MEM_ENT35Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry35 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry35 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry35 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry35 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry35 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry35 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry35 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry35 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:2BB-2B8h (D0F2)
MEM_ENT35Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry35 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry35 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry35 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry35 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry35 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry35 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry35 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry35 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:2BF-2BCh (D0F2)
MEM_ENT35Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry35 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry35 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry35 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME35ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx2BC[10:0]		vcc	x	x	x

Offset Address: 2C3-2C0h (D0F2)
MEM_ENT36Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry36 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry36 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry36 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry36 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry36 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry36 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry36 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry36 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 2C7-2C4h (D0F2)
MEM_ENT36Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry36 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry36 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry36 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry36 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry36 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry36 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry36 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry36 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 2CB-2C8h (D0F2)
MEM_ENT36Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry36 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry36 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry36 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME36ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx2C8[11:0]		vcc	x	x	x

Offset Address: 2CF-2CCh (D0F2)
MEM_ENT37Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry37 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry37 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry37 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry37 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry37 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry37 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry37 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry37 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 2D3-2D0h (D0F2)
MEM_ENT37Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry37 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry37 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry37 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry37 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry37 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry37 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry37 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry37 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37TARGET_LIST8[3:0]		vcc	x	x	x

Offset Address: 2D7-2D4h (D0F2)
MEM_ENT37Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry37 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry37 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry37 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME37ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx2D4[10:0]		vcc	x	x	x

Offset Address: 2DB-2D8h (D0F2)
MEM_ENT38Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry38 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry38 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry38 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry38 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry38 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry38 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry38 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry38 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:2DF-2DCh (D0F2)
MEM_ENT38Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry38 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry38 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry38 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry38 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry38 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry38 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry38 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry38 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:2E3-2E0h (D0F2)
MEM_ENT38Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry38 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry38 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry38 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME38ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx2E0[10:0]		vcc	x	x	x

Offset Address: 2E7-2E4h (D0F2)
MEM_ENT39Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry39 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry39 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry39 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry39 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry39 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry39 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry39 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry39 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 2EB-2E8h (D0F2)
MEM_ENT39Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry39 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry39 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry39 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry39 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry39 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry39 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry39 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry39 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 2EF-2ECh (D0F2)
MEM_ENT39Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry39 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry39 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry39 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME39ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx2EC[11:0]		vcc	x	x	x

Offset Address: 2F3-2F0h (D0F2)
MEM_ENT40Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry40 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry40 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry40 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry40 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry40 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry40 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry40 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry40 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 2F7-2F4h (D0F2)
MEM_ENT40Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry40 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry40 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry40 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry40 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry40 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry40 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry40 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry40 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 2FB-2F8h (D0F2)
MEM_ENT40Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry40 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry40 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry40 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME40ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx12F8[10:0]		vcc	x	x	x

Offset Address: 2FF-2FCh (D0F2)
MEM_ENT41Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry41 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry41 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry41 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry41 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry41 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry41 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry41 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry41 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:303-300h (D0F2)
MEM_ENT41Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry41 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry41 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry41 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry41 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry41 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry41 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry41 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry41 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:307-304h (D0F2)
MEM_ENT41Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry41 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry41 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry41 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME41ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx304[10:0]		vcc	x	x	x

Offset Address: 30B-308h (D0F2)
MEM_ENT42Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry42 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry42 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry42 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry42 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry42 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry42 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry42 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry42 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 30F-30Ch (D0F2)
MEM_ENT42Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry42 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry42 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry42 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry42 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry42 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry42 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry42 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry42 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 313-310h (D0F2)
MEM_ENT42Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry42 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry42 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry42 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME42ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx310[11:0]		vcc	x	x	x

Offset Address: 317-314h (D0F2)
MEM_ENT43Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry43 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry43 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry43 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry43 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry43 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry43 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry43 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry43 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 31B-318h (D0F2)
MEM_ENT43Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry43 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry43 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry43 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry43 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry43 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry43 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry43 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry43 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 31F-31Ch (D0F2)
MEM_ENT43Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry43 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry43 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry43 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME43ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx31C[10:0]		vcc	x	x	x

Offset Address: 323-320h (D0F2)
MEM_ENT44Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry44 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry44 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry44 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry44 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry44 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry44 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry44 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry44 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:327-324h (D0F2)
MEM_ENT44Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry44 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry44 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry44 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry44 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry44 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry44 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry44 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry44 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:32B-328h (D0F2)
MEM_ENT44Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry44 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry44 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry44 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME44ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx328[10:0]		vcc	x	x	x

Offset Address: 32F-32Ch (D0F2)
MEM_ENT45Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry45 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry45 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry45 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry45 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry45 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry45 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry45 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry45 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 333-330h (D0F2)
MEM_ENT45Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry45 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry45 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry45 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry45 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry45 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry45 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry45 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry45 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 337-334h (D0F2)
MEM_ENT45Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry45 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry45 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry45 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME45ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx334[11:0]		vcc	x	x	x

Offset Address: 33B-338h (D0F2)
MEM_ENT46Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry46 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry46 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry46 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry46 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry46 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET _LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry46 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry46 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry46 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address: 33F-33ch (D0F2)
MEM_ENT46Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry46 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry46 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry46 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry46 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry46 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry46 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry46 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry46 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address: 343-340h (D0F2)
MEM_ENT46Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry46 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry46 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry46 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME46ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx340[10:0]		vcc	x	x	x

Offset Address: 347-344h (D0F2)
MEM_ENT47Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry47 TARGET LIST7 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST7[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry47 TARGET LIST6 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST6[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry47 TARGET LIST5 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST5[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry47 TARGET LIST4 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST4[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry47 TARGET LIST3 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST3[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry47 TARGET LIST2 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST2[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry47 TARGET LIST1 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST1[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry47 TARGET LIST0 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST0[3:0]		vcc	x	x	x

Offset Address:34B-348h (D0F2)
MEM_ENT47Default Value: 0000 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:28	RWL	RO	0	MEM entry47 TARGET LIST15 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST15[3:0]		vcc	x	x	x
27:24	RWL	RO	0	MEM entry47 TARGET LIST14 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST14[3:0]		vcc	x	x	x
23:20	RWL	RO	0	MEM entry47 TARGET LIST13 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST13[3:0]		vcc	x	x	x
19:16	RWL	RO	0	MEM entry47 TARGET LIST12 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST12[3:0]		vcc	x	x	x
15:12	RWL	RO	0	MEM entry47 TARGET LIST11 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST11[3:0]		vcc	x	x	x
11:8	RWL	RO	0	MEM entry47 TARGET LIST10 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST10[3:0]		vcc	x	x	x
7:4	RWL	RO	0	MEM entry47 TARGET LIST9 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET_LIST9[3:0]		vcc	x	x	x
3:0	RWL	RO	0	MEM entry47 TARGET LIST8 for target decode ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47TARGET _LIST8[3:0]		vcc	x	x	x

Offset Address:34F-34Ch (D0F2)
MEM_ENT47Default Value: 7FFF E000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31	RWL	RO	0	MEM entry47 attr Indicate the region's memory attribute. 1'b0: Memory; 1'b1: MMIO; ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47ATTR		vcc	x	x	x
30:13	RWL	RO	3FFFFh	MEM entry47 limit addr Memory decoder entry address limit, unit of 256M bytes. 0: means address limit = 256M -1 bytes 1: means address limit = (1+1)x256M – 1 bytes N: means address limit = (N+1)x256M – 1 bytes For an address X, When Base address <= X <= limit address then hit this entry ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47LADDR[45:28]		vcc	x	x	x
12:11	RWL	RO	0	MEM entry47 interleave addr bit sel 2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8] ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) )) ((For Internal Reference: The register is for SVAD.)) ((For Internal Reference: @((#USER=HIF)) ))	RSVAD_ME47ADDR_SEL_11_9		vcc	x	x	x
10:0	RO	NA	0	Reserved	Rx34C[10:0]		vcc	x	x	x

RTopA and LowTopA (350-3FFh)

Offset Address: 353-350h (D0F2)
Highest SVAD limit target to memory (DRAM limit address over 4G)Default Value: FFFF FFC0h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
31:6	RWL	RO	3FFFFFFh	TOP of System memory address over 4G these bits defined the TOP address space over 4G that the system can use as the system memory. The address X of “4G<=X<RTOPA” is the DRAM address. BIOS should set RTOPA = 1000h if no system memory above 4G address This register is used for traffic controller to decode target of the upstream cycle to memory or MMIO(PCI) for P2P ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	RTOPA[45:20]		vcc	x	x	x
5:0	RO	NA	0	Reserved	Rx318[3:0]		vcc	x	x	x

Offset Address: 355-354h (D0F2)
Below 4G highest memory limit(DRAM limit address below 4G)Default Value: FF00h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:4	RWL	RO	FF0h	TOP of System memory address below 4G these bits defined the TOP address space below 4G that the system can use as the system memory. Note: BIOS MUST set Below 4G MMIO Base address = RLOWTOPA = min value of {MMIOB2G, MMIO2T4G} The address X of “X < RLOWTOPA”is the DRAM address. HW use the RLOWTOPA to decode the P2C cycle target to DRAM or MMIO. ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0. @((#control_lock = lock_port RSVAD_LOCK)) ))	RLOWTOPA[31:20]		vcc	x	x	x
3:0	RO	NA	0	Reserved	Rx354[3:0]		vcc	x	x	x

Offset Address: 356-3FFh (D0F2) – Reserved

Offset Address: 320-3FFh (D0F0) – Reserved

TPR Control (400-40Fh)

Offset Address: 400-40Bh (D0F0(D0F2) – Reserved

Offset Address: 40D-40Ch (D0F2)
ReservedDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RO	NA	0	Reserved	Rxcc[15:0]		vcc	x	x	x

Offset Address: 40F-40Eh (D0F2)
TPR ControlDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:5	RO	NA	0	Reserved	Rxce[15:5]		vcc	x	x	x
4	RW	RO	0	APIC Round-Robin Mode Select When enable the round-robin mechanism (RAPICROEN=1), There are two modes to control round-robin method 0: Round-Robin base on each core’s TPR value and select target core 1: Treat all cores as same TPR value and round-robin to select target core, in this case, ignore all TPR value configured from TPR cycle. ((For Internal Reference: @((#TOGGLE=1)) ))	RAPICROMODESEL		vcc	0	x	x
3	RW	NA	0	Reserved ((For Internal Reference: APIC Cluster Model Select There are two ways to decide HIF is in APIC Cluster Model (Note 1) or not. One is auto mode, in this way, HIF will decide whether or not it is in Cluster model according to APIC_CM_EN (Note 2) which is set by CPU’s TPR cycle; the other way is SW control mode, in this way, HIF will decide whether or not it is in Cluster mode according to Register RAPICCMSWEN. 0: Auto mode 1: Software control mode Notes: In logical destination mode, CPU support flat model and Cluster model. Controlled by Destination Format Register in local apic. in Flat model, CPU bit match with Destination field of MSI with Logical APIC ID field in Logical Destination Register of local APIC. The Flat model support up to 8 cores. In Cluster model, the bit [7:4] in Logical APIC ID field is Cluster ID and bit [3:0] in Logical APIC ID field bit match for target cpu cores in this cluster. It support Cluster ID from 0h to Eh, total 15 Cluster ID and support 4 cores in each Cluster ID. Total support 15x4 = 60 cores in Cluster model. When CPU in Cluster model, it will issue TPR cycle with APIC_CM_EN=1. When Cluster ID = Fh, Means broadcast Cluster ID, all CPU treat it as Cluster ID hit. ))	RAPICCMS		vcc	0	x	x
2	RW	NA	0	Reserved ((For Internal Reference: APIC Round-Robin Mechanism Enable When enable the round-robin mechanism, if there are two cores which have the same priority, HIF will not always choose the core which core number is little, but choose the two cores in turn. 0: Disable1: Enable )) ((For Internal Reference: @((#TOGGLE=1)) ))	RAPICROEN		vcc	0	x	x
1	RW	NA	0	Reserved ((For Internal Reference: APIC Cluster Model Software Enable 0: Disable APIC Cluster Model 1: Enable APIC Cluster Model ))	RAPICCMSWEN		vcc	0	x	x
0	RW	NA	0	Reserved ((For Internal Reference: Redirect Lowest Priority MSI Requests to CPU Core0 For supporting the FSB interrupt delivery, this chip is able to redirect the coming in MSI cycle to the CPU with least task priority. This register is used to redirect the Lowest Priority MSI Request cycle to the CPU core0 (CPU0 is treated as the lowest priority processor). 0: Disable. The Lowest Priority MSI Request will be redirected to lowest priority CPU core according to TPR Table record. 1: Enable. The Lowest Priority MSI Request will be always redirected to CPU core0. ))	RAPIC0		vcc	0	0	x

Interrupt Message Address Format

Bit	Description
31:20	always be 0xFEE
19:12	Destination ID
11:4	will always be 0
3	Redirection Hint
2	Destination Mode
1:0	always be 00

Interrupt Message Data Format

Bit	Description
31:16	always be 0000h
15	Trigger Mode
14	Delivery Status
13:12	always be 00
11	always be 0
10:8	Delivery mode
7:0	Vector

DMA Protection Control (410-41Fh)

Offset Address: 411-410h (D0F2)
DMA Protection ControlDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:12	RW	RO	0	Reserved	Rx410[15:12]		vcc	0	x	x
11:4	RWL	RO	0	This is the Size of DPR Region in MB It can be locked by Rx410[0] ((For Internal Reference: This bit is RW when D0F2 DPR_LOCK is set to 0. @((#control_lock = lock_port DPR_LOCK)) ))	DPR_SIZE[7:0]		vcc	*	x	x
3	RW	RO	0	Reserved	Rx410[3]		vcc	0	x	x
2	RWL	RO	0	DPR Enable 0: Disable DPR1: Enable DPR ((For Internal Reference: This bit is RW when D0F2 DPR_LOCK is set to 0. @((#control_lock = lock_port DPR_LOCK)) ))	DPR_EN		vcc	*	x	x
1	RO	NA	0	Reserved	DPR_STS		vcc	0	x	x
0	RWL	RO	0	Lock Bit to Lock DMA Protection Control 0: No effect 1: Bits 11:0 will be locked down in this register. ((For Internal Reference: This bit is RW when D0F2 DPR_LOCK is set to 0. @((#control_lock = lock_port DPR_LOCK)) ))	DPR_LOCK		vcc	0	x	x

Offset Address: 413-412h (D0F2)
ReservedDefault Value: 0000h

Bit	Attribute	HW Property	Default	Description	Mnemonic	ChipRev	PwrDm	S	P	E
15:0	RO	NA	0	Reserved	Rx412[15:0]		vcc	0	x	x

Offset Address: 414-41Fh (D0F2) – Reserved

([TIC Question 1. End of questions. Thanks!])

Revision 00252

IRS Revision History

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IRS Register Attributes

Attribute Definitions

Default Value Definitions

Device 0 Function 2 (D0F2): System SVAD DVAD Controller

PCI Configuration Space

Header Registers (00-3Fh)

Offset Address: 01-00h (D0F2)Vendor IDDefault Value: 1D17h

Offset Address: 03-02h (D0F2)Device IDDefault Value: 31B1h

Offset Address: 05-04h (D0F2)PCI CommandDefault Value: 0006h

Offset Address: 07-06h (D0F2)PCI StatusDefault Value: 02010h

Offset Address: 08h (D0F2)Revision IDDefault Value: 04h

Offset Address: 0B-09h (D0F2)Class CodeDefault Value: 06 0000h

Offset Address: 0Ch (D0F2)Cache Line SizeDefault Value: 00h

Offset Address: 0Dh (D0F2)PCI Master Latency TimerDefault Value: 00h

Offset Address: 0Eh (D0F2)Header TypeDefault Value: 80h

Offset Address: 0Fh (D0F2)Built In Self Test (BIST)Default Value: 00h

Offset Address: 13-10h (D0F2)Base Address Registers 0Default Value: 0000 0000h

Offset Address: 17-14h (D0F2)Base Address Registers 1Default Value: 0000 0000h

Offset Address: 1B-18h (D0F2)Base Address Registers 2Default Value: 0000 0000h

Offset Address: 1F-1Ch (D0F2)Base Address Registers 3Default Value: 0000 0000h

Offset Address: 23-20h (D0F2)Base Address Registers 4Default Value: 0000 0000h

Offset Address: 27-24h (D0F2)Base Address Registers 5Default Value: 0000 0000h

Offset Address: 2B-28h (D0F2)CardBus CIS PointerDefault Value: 0000 0000h

Offset Address: 2D-2Ch (D0F2)Subsystem Vendor IDDefault Value: 0001D170h

Offset Address: 2F-2Eh (D0F2)Subsystem IDDefault Value: 000031B1h

Offset Address: 30h (D0F2)ReservedDefault Value: 00h

Offset Address: 31h (D0F2)ReservedDefault Value: 00h

Offset Address: 32h (D0F2)ReservedDefault Value: 00h

Offset Address: 33h (D0F2)ReservedDefault Value: 00h

Offset Address: 34h (D0F2)Capability PointerDefault Value: 40h

Offset Address: 35h (D0F2)ReservedDefault Value: 00h

Offset Address: 36h (D0F2)ReservedDefault Value: 00h

Offset Address: 37h (D0F2)ReservedDefault Value: 00h

Offset Address: 38h (D0F2)ReservedDefault Value: 00h

Offset Address: 39h (D0F2)ReservedDefault Value: 00h

Offset Address: 3Ah (D0F2)ReservedDefault Value: 00h

Offset Address: 3Bh (D0F2)ReservedDefault Value: 00h

Offset Address: 3D-3Ch (D0F2)Interrupt Line and Interrupt PinDefault Value: 0000h

Offset Address: 3F-3Eh (D0F2)Minimum Grant and Maximum LatencyDefault Value: 0000h

Reserved for PCI Express Capibility (40-7Fh)

Offset Address: 41-40h (D0F0(D0F2)PCI Express ListDefault Value: 8010h

Offset Address: 43-42h (D0F0(D0F2)PCI Express CapabilitiesDefault Value: 0042h

Offset Address: 47-44h (D0F0(D0F2)Device Capabilities 1Default Value: 0000 8000h

Offset Address: 49-48h (D0F0(D0F2)Device Control 1Default Value: 0010h

Offset Address: 4B-4Ah (D0F0(D0F2)Device Status 1Default Value: 0000h

Offset Address: 4F-4Ch (D0F0(D0F2)Link Capabilities 1 Default Value: 0A01 BC41h

Offset Address: 51-50h (D0F0(D0F2)Link Control 1Default Value: 0040h

Offset Address: 53-52h (D0F0(D0F2)Link Status 1Default Value: 1000h

Offset Address: 57-54h (D0F0(D0F2)Slot Capabilities 1Default Value: 0000 0020h

Offset Address: 59-58h (D0F0(D0F2)Slot Control 1Default Value: 0000h

Offset Address: 5B-5Ah (D0F0(D0F2)Slot Status 1Default Value: 0000h

Offset Address: 5D-5Ch (D0F0(D0F2)Root ControlDefault Value: 0000h

Offset Address: 5F-5Eh (D0F0(D0F2)Root CapabilitiesDefault Value: 0000h

Offset Address: 63-60h (D0F0(D0F2)Root StatusDefault Value: 0000 0000h

Offset Address: 67-64h (D0F0(D0F2)Device Capabilities 2Default Value: 0000 0010h

Offset Address: 69-68h (D0F0(D0F2)Device Control 2Default Value: 0000h

Offset Address: 6B-6Ah (D0F0(D0F2)Device Status 2Default Value: 0000h

Offset Address: 6F-6Ch (D0F0(D0F2)Link Capabilities 2Default Value: 0001 0202h

Offset Address: 71-70h (D0F0(D0F2)Link Control 2Default Value: 0000h

Offset Address: 73-72h (D0F0(D0F2)Link Status 2Default Value: 0000h

Offset Address: 74-7Fh (D0F0(D0F2) – Reserved

Reserved for PCI Power Management Capability Structure Registers (80-87h)

Offset Address: 83-80h (D0F0(D0F2)Power Management CapabilitiesDefault Value: C822 0001h

Offset Address: 87-84h (D0F0(D0F2)Power Management Status / ControlDefault Value: 0000 0000h

Reserved Registers (88-8Fh)

Offset Address: 8B-88h (D0F0(D0F2)Reserved ((Internal-RW))Default Value: 0000h

Offset Address: 8F-8Ch (D0F0(D0F2)Reserved ((Internal-RW))Default Value: 0000h

System View Address Decode (90-3FFh)

Offset Address: 01-00h (D0F2)
Vendor IDDefault Value: 1D17h

Offset Address: 03-02h (D0F2)
Device IDDefault Value: 31B1h

Offset Address: 05-04h (D0F2)
PCI CommandDefault Value: 0006h

Offset Address: 07-06h (D0F2)
PCI StatusDefault Value: 02010h

Offset Address: 08h (D0F2)
Revision IDDefault Value: 04h

Offset Address: 0B-09h (D0F2)
Class CodeDefault Value: 06 0000h

Offset Address: 0Ch (D0F2)
Cache Line SizeDefault Value: 00h

Offset Address: 0Dh (D0F2)
PCI Master Latency TimerDefault Value: 00h

Offset Address: 0Eh (D0F2)
Header TypeDefault Value: 80h

Offset Address: 0Fh (D0F2)
Built In Self Test (BIST)Default Value: 00h

Offset Address: 13-10h (D0F2)
Base Address Registers 0Default Value: 0000 0000h

Offset Address: 17-14h (D0F2)
Base Address Registers 1Default Value: 0000 0000h

Offset Address: 1B-18h (D0F2)
Base Address Registers 2Default Value: 0000 0000h

Offset Address: 1F-1Ch (D0F2)
Base Address Registers 3Default Value: 0000 0000h

Offset Address: 23-20h (D0F2)
Base Address Registers 4Default Value: 0000 0000h

Offset Address: 27-24h (D0F2)
Base Address Registers 5Default Value: 0000 0000h

Offset Address: 2B-28h (D0F2)
CardBus CIS PointerDefault Value: 0000 0000h

Offset Address: 2D-2Ch (D0F2)
Subsystem Vendor IDDefault Value: 0001D170h

Offset Address: 2F-2Eh (D0F2)
Subsystem IDDefault Value: 000031B1h

Offset Address: 30h (D0F2)
ReservedDefault Value: 00h

Offset Address: 31h (D0F2)
ReservedDefault Value: 00h

Offset Address: 32h (D0F2)
ReservedDefault Value: 00h

Offset Address: 33h (D0F2)
ReservedDefault Value: 00h

Offset Address: 34h (D0F2)
Capability PointerDefault Value: 40h

Offset Address: 35h (D0F2)
ReservedDefault Value: 00h

Offset Address: 36h (D0F2)
ReservedDefault Value: 00h

Offset Address: 37h (D0F2)
ReservedDefault Value: 00h

Offset Address: 38h (D0F2)
ReservedDefault Value: 00h

Offset Address: 39h (D0F2)
ReservedDefault Value: 00h

Offset Address: 3Ah (D0F2)
ReservedDefault Value: 00h

Offset Address: 3Bh (D0F2)
ReservedDefault Value: 00h

Offset Address: 3D-3Ch (D0F2)
Interrupt Line and Interrupt PinDefault Value: 0000h

Offset Address: 3F-3Eh (D0F2)
Minimum Grant and Maximum LatencyDefault Value: 0000h

Offset Address: 41-40h (D0F0(D0F2)
PCI Express ListDefault Value: 8010h

Offset Address: 43-42h (D0F0(D0F2)
PCI Express CapabilitiesDefault Value: 0042h

Offset Address: 47-44h (D0F0(D0F2)
Device Capabilities 1Default Value: 0000 8000h

Offset Address: 49-48h (D0F0(D0F2)
Device Control 1Default Value: 0010h

Offset Address: 4B-4Ah (D0F0(D0F2)
Device Status 1Default Value: 0000h

Offset Address: 4F-4Ch (D0F0(D0F2)
Link Capabilities 1 Default Value: 0A01 BC41h

Offset Address: 51-50h (D0F0(D0F2)
Link Control 1Default Value: 0040h

Offset Address: 53-52h (D0F0(D0F2)
Link Status 1Default Value: 1000h

Offset Address: 57-54h (D0F0(D0F2)
Slot Capabilities 1Default Value: 0000 0020h

Offset Address: 59-58h (D0F0(D0F2)
Slot Control 1Default Value: 0000h

Offset Address: 5B-5Ah (D0F0(D0F2)
Slot Status 1Default Value: 0000h

Offset Address: 5D-5Ch (D0F0(D0F2)
Root ControlDefault Value: 0000h

Offset Address: 5F-5Eh (D0F0(D0F2)
Root CapabilitiesDefault Value: 0000h

Offset Address: 63-60h (D0F0(D0F2)
Root StatusDefault Value: 0000 0000h

Offset Address: 67-64h (D0F0(D0F2)
Device Capabilities 2Default Value: 0000 0010h

Offset Address: 69-68h (D0F0(D0F2)
Device Control 2Default Value: 0000h

Offset Address: 6B-6Ah (D0F0(D0F2)
Device Status 2Default Value: 0000h

Offset Address: 6F-6Ch (D0F0(D0F2)
Link Capabilities 2Default Value: 0001 0202h

Offset Address: 71-70h (D0F0(D0F2)
Link Control 2Default Value: 0000h

Offset Address: 73-72h (D0F0(D0F2)
Link Status 2Default Value: 0000h

Offset Address: 83-80h (D0F0(D0F2)
Power Management CapabilitiesDefault Value: C822 0001h

Offset Address: 87-84h (D0F0(D0F2)
Power Management Status / ControlDefault Value: 0000 0000h

Offset Address: 8B-88h (D0F0(D0F2)
Reserved ((Internal-RW))Default Value: 0000h

Offset Address: 8F-8Ch (D0F0(D0F2)
Reserved ((Internal-RW))Default Value: 0000h

Offset Address: 93-90h (D0F2)
MMIOCFG decoderDefault Value: 0nnn nn00h

Offset Address: 97-94h (D0F2)
MMIOCFG limit addressDefault Value:nnnn nnnnh

Offset Address: 9B-98h (D0F2)
MMIOCFG limit addressDefault Value: nnnn nnnnh

Offset Address: 9F-9Ch (D0F2)
MMIOCFG limit addressDefault Value: nnnn nnnnh

Offset Address: A3-A0h (D0F2)
MMIOCFG limit addressDefault Value: nnnn nnnnh

Offset Address: A7-A4h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Offset Address: AB-A8h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Offset Address: AF-ACh (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Offset Address: B3-B0h (D0F2)
MMIOB2G decoder Default Value:0000 0000h

Offset Address: B7-B4h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h

Offset Address: BB-B8h (D0F2)
MMIO2T4G decoderDefault Value:0000 0000h

Offset Address: BF-BCh (D0F2)
MMIO2T4G decodeDefault Value:0000 0000h

Offset Address: C3-C0h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h

Offset Address: C7-C4h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h

Offset Address: CB-C8h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h

Offset Address: CF-CCh (D0F2)
ABSEGDefault Value: 0000 0000h

Offset Address: D3-D0h (D0F2)
C/D/E/F SEGDefault Value: 0000 0000h

Offset Address: D7-D4h (D0F2)
MMIO and VGA IO decoderDefault Value: 0000 0000h

Offset Address: DB-D8h (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Offset Address: DF-DCh (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Offset Address: E3-E0h (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Offset Address: E7-E4h (D0F2)
legacy IO decoderDefault Value: 0000 0000h

Offset Address: E9-E8h (D0F2)
Multi-die link readyDefault Value: 0000h