Internal Register Set

CHX0023

North Module

Bus 0 Device 0 Function 2

SVAD DVAD Control

Revision 00252
July 10, 2019March 7, 2019

Shanghai Zhaoxin Semiconductor

IRS Revision History

Doc Rev.Chip Rev.DateRevision DescriptionsDepartmentName
R052A07/9/2019
  1. Change Rx90[31:28] HW attr to RO
  2. Change RxB8[31:3] SW attr to RO and HW attr to NA
  3. Correct default value for RSVAD_MEXXLADDR[45:28] and RTopA
  4. Correct some description
NBChunhui Zheng
R051A06/25/2019Update SVAD according to SW review resultCPUSharon Gao
R050A06/14/2019Update PCI Config space FigureNBChunhui Zheng
R003A03/15/2019
  1. add RSVAD_MMIOB2G_DIS at Rx9C[1]
NBChunhui Zheng
R002A043/148/20179
  1. add PCIE capability and Power Management Capability
  2. move SVAD register to Rx90h~Rx3FFh, TPR start offset to Rx400h
  3. Remove DVAD registers
  4. Add legacy IO decoder by Sharon
  5. Add DPR control
NBChunhui Zheng
R001A03/6/2019Initial internal release based on CHX002CPUSharon Gao

Lists of TIC Tags

TIC Question Tag

([TIC Question 1. End of questions. Thanks!])63

TIC Editing Tag

([ TIC Editing Note 1. The default value should be changed to nnnnh in SPM. ])12

Table of Contents

IRS Revision History1

Lists of TIC Tags2

TIC Question Tag2

TIC Editing Tag2

Table of Contents3

List of Tables4

List of Figures4

IRS Style Brief Introduction (For IRS Rule V3.R3)5

Tags and Colors5

Columns of The Register Table5

Columns of Suggested Values:5

IRS Register Attributes7

Attribute Definitions7

Default Value Definitions8

Device 0 Function 2 (D0F2): System SVAD DVAD Controller9

PCI Configuration Space9

Header Registers (00-3Fh)12

System View Address Decode (40-BFh)19

TPR Control (C0-CFh)51

DRAM View Address Decode (D0-EFh)54

List of Tables

Table 1. SVAD Decode for SMM47

List of Figures

Figure 1. System Block Diagram for D0F29

Figure 2. Register Level Block Diagram for D0F29

IRS Style Brief Introduction (For IRS Rule V3.R3)

Tags and Colors

To distinguish different levels of confidentiality, TIC uses “tags” and “colors” to identify registers with different purposes. Each of them represents different meanings.

Tags and Colors Used by TIC

How to use Highlight:

  1. Enable [View] > [Tool Bar] > [Table and Border], and you will see an icon of a paint-bucket shown in tool bar for the Shading-Filling tool. If you cannot see it, do the next step.
  2. From [View] > [Tool Bar] > [Customize], select [Commands] > Categories = [Borders], Commands = [Border and Shading]. Draw that item to tool bar. Apply it to some text. Go back to step 1. You should be able to see that icon then.
  3. Or you can select the icon from [Commands] > [All Commands] > Shading-Color.

Columns of The Register Table

The Suggestion Values:


IRS Register Attributes

Attribute Definitions

Basic Attributes: indicate common read-write operations.

RO:Read Only.

WO:Write Only. (register value can not be read by the software)

RW:Read / Write.

RW1:Write Once then Read Only after that.

RW1C:Read / Write of “1” clears bit to zero.

RWL:Lockable Read / Write. Read/writable with lock bit control: RW when lock bit=0, Read-Only when lock bit=1.

Extended Attributes: indicate combinational or internal access methods.

RO((shadow)): Value of this register is copied from another register.

RO((RW)):Used to indicate the existence of the internal guard bit.

RO/RW:Used to indicate the public guard bit. (ex. if the guard bit is defined in spec)

RW((RWHC)): R/W-able with hardware clear automatically.

Sticky Attributes:

Adding an “S” in tail indicates a sticky register, which means that register will not be set or altered by hot reset.

Adding the RS in tail indicates a reset-sticky register, which means that register will not be reset unless the system entered S4/S5 state.

ROS: Sticky-Read-Only.

WOS: Sticky-Write-Only.

RWS: Sticky-Read/Write.

RW1S:Sticky-Write-Once.

RW1CS:Sticky-Write-1-to-Clear.

RWLS:Sticky-Lockable Read/Write.

RORS: Reset-Sticky-Read-Only.

WORS:Reset-Sticky-Write-Only.

RWRS: Reset-Sticky-Read/Write.

RW1RS:Reset-Sticky-Write-Once.

RW1CRS: Reset-Sticky-Write-1-to-Clear.

ROS((shadows)):Sticky-shadow

ROS((RWS)):Sticky-RO((RW))

ROS/RWS:Sticky-RO/RW

RW((RWHC))S: Sticky-RW((RWHC))

RORS((shadows)):Reset-Sticky-shadow

RORS((RWS)):Reset-Sticky-RO((RW))

RORS/RWRS:Reset-Sticky-RO/RW

RW((RWHC))RS:Reset-Sticky-RW((RWHC))

((Internal Notes:

1. For RW1Set in xHCI spec: per discussion, it is the same with RW((RWHC)).

RW1Set: Read / Write of “1” sets bit to “1”. (Writing a 0 has no effect)

RW1SetS: Sticky-Write-1-to-Set ))

Default Value Definitions

Dip:Means the default value is set by dip switch or strapping.

HwInit:Hardware initialized; bit default value is set by hardware to reflect related status.

ROMSIP: The default will be overwritten by the value defined in ROMSIP after system reset.

(( Bonding: The default value depends on different product. ))

Device 0 Function 2 (D0F2): System SVAD DVAD Controller

@((SOURCE: CHIP_SRC=CHX0022(A0), DOC_SRC= CHX0023 IRS_NB_D0F2_SVADDVAD_R0013, IRS_STYLE_VER=V3 ))

@((MODULE(MOD_D0F2, 1x1): PRJ=CHX0023, REG_SPACE_NUM=1, ADDR_WIDTH=12 ))

@((REG_SPACE [0]: TYPE=PCI, NAME=D0F2, SEL=AD11, SPACE_LEVEL=1, RANGE=(0h, FFFh) ))

@((DEFAULT_GUARDBIT=RPEROWEN D0F5 RXF0[0]))

@((REG_GROUP(PCI Header Registers): RANGE=(0h, 3Fh) ))

PCI Configuration Space

This chip integrates the functions of conventional chipset North Bridge, South Bridge and the Graphics Controller (GFXCTL) into one single chip. The traditional functions of North Bridge is included in the North Module (NM) of this chip; while the functions of traditional South Bridge, like PCI bus controller and ISA controller, are included in the South Module (SM) of this chip, as shown in Figure 1 below.

Device 0 Function 2 is a Host Bridge. All registers in this function are located in PCI configuration space and should be programmed using PCI configuration mechanism 1 through I/O registers CF8 / CFC with bus number 0, device number 0 and function number 2. For example, I/O write CF8h, with the data having the following format. And then I/O read CFCh, to get the data or I/O write CFCh, to write data (32 bits). Registers in this function can also be accessed using PCIE enhanced configuration mechanism when it is enabled by programming D0F2Rx40[17:0].

Bit [31]Bits [30:24]Bits [23:16]Bits [15:11]Bits [10:8]Bits [7:2]Bit [1]Bit [0]
EnableReservedBus NumberDevice NumberFunction NumberRegister Number00
1000_00000000_00000_0000010RX offset address with bit [1:0] = 00b


Figure 1. System Block Diagram for D0F2

Figure 2. Register Level Block Diagram for D0F2


Header Registers (00-3Fh)

Rx00-Rx3F are PCI header registers. Please refer to PCI specification for more information.

([ TIC Editing Note 1. The default value should be changed to nnnnh in SPM. ])

Offset Address: 01-00h (D0F2)
Vendor IDDefault Value: 1D17h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:0RO((RWL))NA1D17hVendor ID
Used to identify the manufacturer of this device.
((For Internal Reference: @((#USER=PCISPEC))
@((#control_lock=lock_port D0F2_RX40B29RVID_DID_LOCK_D0F2))
@((#control_default=NB_VID_SEL))
@((#VENDOR_OPTION=1106h))
))
VendorID[15:0]vccxxx
Offset Address: 03-02h (D0F2)
Device IDDefault Value: 31B1h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:0RO((RWL))NA31B1hDevice ID
Used to identify this function.
((For Internal Reference: @((#USER=PCISPEC))
@((#control_lock=lock_port D0F2_RX40B31RDID_RID_LOCK_D0F2))
))
DEVID[15:0]vccxxx
Offset Address: 05-04h (D0F2)
PCI CommandDefault Value: 0006h

The bit values of this register are fixed and they do not affect any behavior on the PCI bus. ((For Internal Reference: The behavior of the PCI bus is controlled by the PCI command registers on D17F7 (when D17F7Rx4F[6](RENPPB) = 0) or D19F0 (when D17F7Rx4F[6](RENPPB) = 1).))

BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:10RONA0ReservedRx04[15:10]vccRxx
9RONA0Fast Back-to-back Cycle Enable
It is used to enable the fast back-to-back capability on the PCI bus for the PCI bus controller.
RFBACKvccRxx
8RONA0SERR# Enable
It is used to enable the SERR# driver which asserts SERR# signal on the PCI bus.
RSERRvccRxx
7RONA0Address/Data Stepping
It is used to enable the address/data stepping for PCI bus controller to generate cycles on the PCI bus.
RSETPvccRxx
6RONA0Parity Error Response
It is used to tell the PCI bus controller to perform the parity check on the PCI bus or not.
*RPTYERRvccRxx
5RONA0VGA Palette Snooping
It controls how VGA compatible Graphics devices handle accesses to VGA palette registers.
This bit is fixed at 0.
RVGAvccRxx
4RONA0Memory Write and Invalidate
It is used to enable the PCI bus controller to issue Memory Write Invalidate command on the PCI bus.
RMWINVvccRxx
3RONA0Respond to Special Cycle
It is used to enable the PCI bus controller to take actions once it sees a special cycle on the PCI bus.
RSPCYCvccRxx
2RONA1bPCI Master Function
It is used to enable the PCI bus controller to issue cycles to devices on the PCI bus.
RMSTRvccRxx
1RONA1bMemory Space Access
It is used to enable the PCI bus controller to accept the memory cycles from devices on the PCI bus.
RENMEMvccRxx
0RONA0I/O Space Access
It is used to enable the PCI bus controller to accept the I/O cycles from devices on the PCI bus.
RENIOvccRxx
Offset Address: 07-06h (D0F2)
PCI StatusDefault Value: 02010h

The value of this register won’t reflect what happened on the PCI bus. ((For Internal Reference: The status of the PCI bus is reported to the PCI Status Register at D17F7 (when D17F7 Rx4F[6](RENPPB) = 0) or D19F0 (when D17F7 Rx4F[6](RENPPB) = 1).))

BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15RONA0Detected Parity Error
It is used to indicate a parity error had been detected by the PCI bus controller.
SPERRSvccRxx
14RONA0Signaled System Error (SERR# Asserted)
It is used to indicate the PCI bus controller had asserted the SERR#.
SERRSvccRxx
13RONA0Received Master-abort (Except Special Cycle)
It is used to indicate the PCI bus controller encountered a cycle termination by master abort for its transaction.
SMABORTvccRxx
12RONA0Received Target-abort
It is used to indicate the PCI bus controller encountered a cycle termination by target abort for its transaction.
STABORTMvccRxx
11RONA0Target-abort Assertion
It is used to indicate the PCI bus controller issued a target abort termination for the cycle targeted to it.
STABORTSvccRxx
10:9RONA01bDEVSEL# Timing
It is used to indicate the response latency for the timing of PCI signal DEVSEL#.
00: Fast01: Medium
10: Slow11: Reserved
These bits won’t affect the DEVSEL# timing on the PCI bus.
DEVS[1:0]vccRxx
8RONA0Master Data Parity Error
It is used to tell that PERR# on the PCI bus is asserted to indicate a possible parity error happened. It includes three cases:
  1. As a target, the PCI bus controller asserts PERR# on a read cycle or observes the assertion of PERR# on a write cycle.
  2. As a initiator, the PCI bus controller encounters error upon the cycle it initiates.
  3. Parity Error Response bit at Rx04[6](RPTYERR) is set.
SDPERRSvccRxx
7RONA0Capable of Accepting Fast Back-to-back as a Target
It is used to indicate the capability of accepting fast back-to-back cycles.
RFBKSvccRxx
6RONA0User Definable Features
It is reserved for user to define.
RUDFvccRxx
5RONA066MHz Capability
It is used to indicate the capability of supporting 66Mhz for the PCI bus controller.
((For Internal Reference: @((EXT = ECO)) ))
R66MvccRxx
4RONA1b0Support New Capability List
It indicates whether this device implements the pointer for a New Capabilities linked list at offset 34h.
0: New capability linked list is not available.
1: The value read at offset 34h is a pointer in configuration space to a linked list of new capabilities, i.e., new capability linked list is supported.
RCAPvccRxx
3:0RONA0ReservedRx04[19:16]vccRxx

Offset Address: 08h (D0F2)
Revision IDDefault Value: 04h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RO((RWL))NA04hRevision Code
It indicates the revision ID of this function.
((For Internal Reference: @((#USER=PCISPEC))
@((#control_lock=lock_port D0F2_RX40B31RDID_RID_LOCK_D0F2))
))
Rx08[7:0]vccxxx
Offset Address: 0B-09h (D0F2)
Class CodeDefault Value: 06 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
23:0RO((RWL))NA06 0000hClass Code
06 0000h indicates this function is a host bridge.
((For Internal Reference: @((#USER=PCISPEC)) @((#control_lock=lock_port D0F2_RX40B27RCLASS_CODE_LOCK_D0F2)) ))
ClassCode[23:0]vccxxx
Offset Address: 0Ch (D0F2)
Cache Line SizeDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RWNA0Cache Line Size
It indicates the cache-line size in a cache-line transaction in units of double words.
((Writing 1 or 0 to these registers does not change any behavior of this chip.))
((For Internal Reference: Some HCT software requires these registers to be R/W to have warning free report.))
Rx0C[7:0]vccxxx
Offset Address: 0Dh (D0F2)
PCI Master Latency TimerDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0Maximum Time Slice for This Function as a Master on the PCI Bus
It indicates how many PCI clocks of duration the PCI controller as a master can own the PCI bus. The unit is 8 PCI Clocks. They do not have any impact to the behaviors of this chip.
Rx0C[15:8]vccRxx
Offset Address: 0Eh (D0F2)
Header TypeDefault Value: 80h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA80hHeader Type
Bit [7] in this register is used to identify a multifunction device. If bit [7] = 0, the device is single function. If bit [7] = 1, the device is multiple functions. Bits [6:0] identify the layout of the second part of the predefined header. 00h is the header type for this host bridge. The value 80h indicates that this is a multi-function device.
Rx0C[23:16]vccRxx
Offset Address: 0Fh (D0F2)
Built In Self Test (BIST)Default Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0BIST Support
Bit [7] = 0 indicates that this function does not support BIST. Writing a 1 to bit [6] will invoke the BIST operation. The value of 0h on bits [3:0] means the device has passed its test. Non-zero values on bits [3:0] means the device failed. This chip does not support BIST through these registers.
Rx0C[31:24]vccRxx
Offset Address: 13-10h (D0F2)
Base Address Registers 0Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RONA0Base Address 0
This function does not claim base address.
Rx10[31:0]vccRxx
Offset Address: 17-14h (D0F2)
Base Address Registers 1Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RONA0Base Address 1
This function does not claim base address.
Rx14[31:0]vccRxx
Offset Address: 1B-18h (D0F2)
Base Address Registers 2Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RONA0Base Address 2
This function does not claim base address.
Rx18[31:0]vccRxx
Offset Address: 1F-1Ch (D0F2)
Base Address Registers 3Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RONA0Base Address 3
This function does not claim base address.
Rx1C[31:0]vccRxx
Offset Address: 23-20h (D0F2)
Base Address Registers 4Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RONA0Base Address 4
This function does not claim base address.
Rx20[31:0]vccRxx
Offset Address: 27-24h (D0F2)
Base Address Registers 5Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RONA0Base Address 5
This function does not claim base address.
Rx24[31:0]vccRxx
Offset Address: 2B-28h (D0F2)
CardBus CIS PointerDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RONA0CardBus CIS Pointer
This field is used to point to the Card Information Structure (CIS) for the CardBus Card. It is not supported by this function.
Rx28[31:0]vccRxx
Offset Address: 2D-2Ch (D0F2)
Subsystem Vendor IDDefault Value: 0001D170h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:0RW1NA01D17hSubsystem Vendor ID
They are used to uniquely identify the manufacturer of the expansion board or subsystem where the PCI device resides. These write once registers can be written once and only once after the de-assertion of PCIRST#.
Rx2C[15:0]vccxxx
Offset Address: 2F-2Eh (D0F2)
Subsystem IDDefault Value: 000031B1h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:0RW1NA031B1hSubsystem ID
They are used to uniquely identify the expansion board or subsystem where the PCI device resides. These write once registers can be written once and only once after the de-assertion of PCIRST#.
Rx2C[31:16]vccxxx
Offset Address: 30h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx30[7:0]vccRxx
Offset Address: 31h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx31[7:0]vccRxx
Offset Address: 32h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx32[7:0]vccRxx
Offset Address: 33h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx33[7:0]vccRxx
Offset Address: 34h (D0F2)
Capability PointerDefault Value: 40h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RO((RW))NA40hCapability List Pointer
It indicates an offset address from the start of the configuration space. This pointer points to a linked list of new capabilities implemented by this device. A 0 indicates the end of the list. This function of this chip does not have any capability needed to be specified.
CAPPTR[7:0]vcc40hxx
Offset Address: 35h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx35[7:0]vccRxx
Offset Address: 36h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx36[7:0]vccRxx
Offset Address: 37h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx37[7:0]vccRxx
Offset Address: 38h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx38[7:0]vccRxx
Offset Address: 39h (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx39[7:0]vccRxx
Offset Address: 3Ah (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx3A[7:0]vccRxx
Offset Address: 3Bh (D0F2)
ReservedDefault Value: 00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
7:0RONA0ReservedRx3B[7:0]vccRxx
Offset Address: 3D-3Ch (D0F2)
Interrupt Line and Interrupt PinDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:8RONA0Interrupt Pin
It tells which interrupt pin the device uses. It is not applicable to this function.
Rx3C[15:8]vccRxx
7:0RONA0Interrupt Line
It is used to communicate interrupt line routing information. It is not applicable to this function.
Rx3C[7:0]vccRxx
Offset Address: 3F-3Eh (D0F2)
Minimum Grant and Maximum LatencyDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:8RONA0Maximum Latency
It is used to specify how often the device needs to gain access to the PCI bus in units of 1/4 microsecond. It is not applicable to this function.
Rx3C[31:24]vccRxx
7:0RONA0Minimum Grant
It is used to specify how long a burst period this device needs in units of 1/4 microsecond. It is not applicable to this function.
Rx3C[23:16]vccRxx

@((REG_GROUP(Multi-Function Control and Legacy Space Access Control): RANGE=(40h, 7Fh) ))

Reserved for PCI Express Capibility (40-7Fh)

Offset Address: 41-40h (D0F0(D0F2)
PCI Express ListDefault Value: 8010h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:8RO((RW))NA80hNext Pointer
This 8-bit pointer points to the next capability of this function. Next capability is resided started from Rx88h
RX40[15:8]vcc80hxx
7:0RONA10hCapability ID
This byte is read as 10h indicates a PCI Express Capability Structure.
RX40[7:0]vcc10hxx
Offset Address: 43-42h (D0F0(D0F2)
PCI Express CapabilitiesDefault Value: 0042h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:14RONA0ReservedRX42[15:14]vcc0xx
13:9RO((RW))NA0Interrupt Message NumberRX42[13:9]vcc0xx
8RO((RW))NA0Slot ImplementedRX42[8]vcc0bxx
7:4RO((RW))NA0100bDevice / Port TypeRX42[7:4]vcc0100bxx
3:0RO((RW))NA2hCapability Version BitRX42[3:0]vcc2hxx
Offset Address: 47-44h (D0F0(D0F2)
Device Capabilities 1Default Value: 0000 8000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:29RONA0Reservedrsv_19vccRxx
28RO
((RW))
NA0Function Level Reset Capability
A value of 1 indicates this function supports the optional Function Level Reset (FLR) mechanism. This field applies to Endpoints only.
It is reserved for this root port.
((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))
tbd_27vcc0xx
27:26RONA0Captured Slot Power Limit Scale
This field specifies the scale used for the Slot Power Limit Value (Rx44[25:18]).
Range of values:
00: 1.0x.01: 0.1x.
10: 0.01x.11: 0.001x.
Upon receiving the Set_Slot_Power_Limit Message from the upper link, this field is set as the value specified in the message or is hardwired to 00b.
This bit is for upstream port only, it is reserved and always read as 00b for this root port.
rsv_20vcc0xx
25:18RONA0Captured Slot Power Limit Value
In combination with the Slot Power Limit Scale value (Rx44[27:26]), this field specifies the upper limit on power supplied by slot. Power limit (in Watts) calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field (Rx44[27:26]). Upon receiving the Set_Slot_Power_Limit Message from the upper link, this field is set as the value specified in the message or is hardwired to 00h.
This bit is for upstream port only, it is reserved and always read as 00h for this root port
rsv_21vcc0xx
17:16RONA0Reservedrsv_22vccRxx
15RO
((RW))
NA1bRole-based Error Reporting
When set to 1, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1.
0: Role-based error reporting is not supported.
1: Role-based error reporting is supported.
((For Internal Reference: This chip does NOT fully support Role-Base Error reporting. It implemented the way to change the Non-fatal error to become correctable error in the system. However, the default value is 1 for passing Microsoft WLK test. Microsoft treat the root port support Role-Based Error Reporting as support PCIe 1.1.
This bit becomes write-able when D0F5 RxF0[0] is programmed to 1.))
RRBERRPvcc1xx
14RONA0Power Indicator Present
When set to 1, this bit indicates that a Power Indicator is implemented on the adapter and is electrically controlled by the component on the adapter using the Power_Indicator_On, Power_Indicator_Blink, and Power_Indicator_Off Messages.
It is reserved for root port.
Note: According to PCIE GEN3 SPEC, the value read from this bit is undefined.
rsv_23vcc0xx
13RONA0Attention Indicator Present
When set to 1, this bit indicates that an Attention Indicator is implemented on the adapter and is electrically controlled by the component on the adapter using the Attention_Indicator_On, Attnetion_Indicator_Blink, and Attention_indicator_Off Messages.
It is reserved for root port.
Note: According to PCIE GEN3 SPEC, the value read from this bit is undefined.
rsv_24vcc0xx
12RONA0Attention Button Present
When set to 1, this bit indicates that an Attention Button is implemented on adapter and is electrically controlled by the component on the adapter. Attention Button press events are reported using the Attention_Button_Pressed Message.
It is reserved for root port.
Note: According to PCIE GEN3 SPEC, the value read from this bit is undefined.
rsv_25vcc0xx
11:9RO
((RW))
NA000bEndpoint L1 Acceptable Latency
This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.
000: 1us001: 2us
010: 4us011: 8us
100: 16us101: 32us
110: 64us111: No limit
It is reserved for root port.
((For Internal Reference: It is reserved for Root Port and supposed to be always 000b. And this bit becomes write-able when D0F5 RxF0[0] is programmed to 1.))
DAL1AL_ vcc0xx
8:6RONA0Endpoint L0s Acceptable Latency
This field indicates the acceptable total latency that an Endpoint can withstand due to the transition for L0s state to L0 State.
000: 64ns001: 128ns
010: 256ns011: 512ns
100: 1024ns101: 2us
110: 4us111: No limit
It is reserved for root Port.
Rsv_44vcc0xx
5RO
((RW))
NA0Extended Tag Field Supported
This bit indicates the maximum supported size of the tag field as a requester.
0: 5-bit tag field supported.
1: 8-bit tag field supported.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
*DAXTAGFvcc0xx
4:3RONA0Phantom Functions Supported
This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the tag identifier. This field indicates the number of most significant bits of the function number portion of Requester ID that are logically combined with the tag identifier.
00: No function number bits used for Phantom Functions. That is, the Tag field of the requester remain at 8 bits.
01: First MSB of function number in Requester ID used for Phantom Functions. That is, MSB bit can be combined with the transaction Tag to form a 9 bits Tag to track the outstanding transactions.
10: First 2 MSB of function number in Requester ID used for Phantom Functions. That is, 2 MSB bits can be combined with the transaction Tag to form a 10 bits Tag to track the outstanding transactions.
11: All three bits of function number in Requester ID used for Phantom Functions. That is, all 3 function bits can be combined with the transaction Tag to form a 11 bits Tag to track the outstanding transactions.
This chip does not support the Phantom Functions.
rsv_26vcc0xx
2:0RO
((RW))
NA000bMax Payload Size Supported
This field indicates the maximum payload size that this root port can support for the upstream write requests.
000: 128 bytes (16 QW)
001: 256 bytes (32 QW)
010: 512 bytes (64 QW)
011: 1024 bytes (128 QW)
100: 2048 bytes (256 QW)
101: 4096 bytes (512 QW)
110, 111: Reserved.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
DAMPSS_ vcc000bxx
Offset Address: 49-48h (D0F0(D0F2)
Device Control 1Default Value: 0010h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15RONA0Reservedrsv_27vccRxx
14:12RONA0Max Read Request Size
This field sets the maximum Read Request size for the device as a Requestor.
000: 128 bytesOthers: Reserved
DCMRRS_ vcc0xx
11RWNA0Enable No Snoop
0: Disable1: Enable
If this bit is set to 1, the device is permitted to set the No Snoop bit in the Requestor Attributes of the transactions to indicate that it does not require hardware enforced cache coherency.
DCENSvcc0xx
10RWNA0Auxiliary Power PM Enable
0: Disable1: Enable
This bit when set enables device to draw AUX power independent of PME AUX power.
DCAPPMEvcc0xx
9RONA0Phantom Functions EnableDCPFEvcc0xx
8RO/RWNA0Extended Tag Field Enable
When Rx44[5] (DAXTAGF) is set to 0, this bit is RO.
When Rx44[5] (DAXTAGF) is set to 1, this bit is RW.
((For Internal Reference: This bit is RW when D0F02 Rx44[5] is set to 1.))
@((guardbit=DAXTAGF D0F02 RX44[5]))
DCETFEvcc0xx
7:5RWNA0Max Payload Size
Maximum TLP payload size.
000: 128bytes001: 256 bytes
Others: Reserved
DCMPS_ vcc000000x
4RWNA1bEnable Relaxed Ordering
0: Disable1: Enable
If this bit is set to 1, the device is permitted to set the Relaxed Ordering bit in the Requestor Attributes of the transactions to indicate that it does not require strong write ordering.
DCEROvcc1xx
3RWNA0Unsupported Request Reporting Enable
0: Disable1: Enable
((For internal verify reference: @((#TOGGLE=1)) ))
DCURREvcc0xx
2RWNA0Fatal Error Reporting Enable
0: Disable1: Enable
For a root port, the report of Fatal errors is internal to the root. No external ERR_FATAL message is generated.
((For internal verify reference: @((#TOGGLE=1)) ))
DCFEREvcc0xx
1RWNA0Non-Fatal Error Reporting Enable
0: Disable1: Enable
For a root port, the report of Non-Fatal errors is internal to the root. No external ERR_NONFATAL message is generated.
((For internal verify reference: @((#TOGGLE=1)) ))
DCNFEREvcc0xx
0RWNA0Correctable Error Reporting Enable
0: Disable1: Enable
For a root port, the report of correctable errors is internal to the root. No external ERR_COR message is generated.
((For internal verify reference: @((#TOGGLE=1)) ))
DCCEREvcc0xx
Offset Address: 4B-4Ah (D0F0(D0F2)
Device Status 1Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:6RONA0ReservedRsv_4bvccRxx
5RONA0Transactions Pending
This bit when set indicates that the port has issued Non-Posted Requests on its own behalf (using the Requestor ID of the Port) which have not been completed.
DSTPvcc0xx
4RO
((RW))
NA0AUX Power Detected
0: Not detected1: Detected
((For Internal Reference: RW/RO through D0F5 RxF0[0].))
DSAPDvcc0xx
3RONA0Unsupported Request Detected (TL)
0: Not detected1: Detected
DSURDvcc0xx
2RONA0Fatal Error Detected (TL)
0: Not detected1: Detected
DSFEDvcc0xx
1RONA0Non-Fatal Error Detected (TL)
0: Not detected1: Detected
DSNFEDvcc0xx
0RONA0Correctable Error Detected (TL)
0: Not detected1: Detected
DSCEDvcc0xx
Offset Address: 4F-4Ch (D0F0(D0F2)
Link Capabilities 1 Default Value: 0A01 BC41h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:24RO
((RW))
NA0AhPort Number
This field indicates the PCI Express Port number for the given PCI Express Link.
((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))
LKPN_ vccxxx
23:22RONA0Reservedrsv_31vccRxx
21RO
((RW))
NA0Link Bandwidth Notification Capability
This bit indicates support for the Link Bandwidth Notification status and interrupt mechanism.
((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))
RLBWNTFCvcc0bxx
20RO
((RW))
NA0Data Link Layer Link Active Reporting Capable
This bit indicates support of reporting the DL_Active state of DLCMSM.
((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))
RDL_AR_CAPvcc0bxx
19RO
((RW))
NA0Surprise Down Error Reporting Capable
This bit indicates support of detecting and reporting a Surprise Down error condition.
((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))
RLCASDERCvcc0bxx
18RONA0Clock Power ManagementRLCACPMvcc0xx
17:15RO
((RW))
NA011bL1 Exit Latency
This field indicates the L1 exit latency (to L0) for the given PCIe Link.
Defined encoding for this latency Tl_L1 are:
000: Tl_L1 < 1us
001: 1us <= Tl_L1< 2us
010: 2us <= Tl_L1 < 4us
011: 4us <= Tl_L1 < 8us
100: 8us <= Tl_L1 < 16us
101: 16us <= Tl_L1 < 32us
110: 32us <= Tl_L1 < 64us
111: 64us <= Tl_L1
((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))
LKL1EL_ vccxxx
14:12RO((RW))NA011bL0s Exit Latency
This field indicates the L0s exit latency (to L0) for the given PCIe Link.
Read return value is from following registers:
D2F4 RxE1[2:0] when PE3 in 2.5G/Ts speed.
D2F4 RxE2[2:0] when PE3 in 5.0G/Ts speed.
LKL0SE_ vccxxx
11:10RO
((RW))
NA11bActive State Link PM (ASPM) Support
11b: L0s and L1 supported.
((For Internal Reference: RW when D0F5 RxF0[0] is set to 1.))
LKAPMS_ vcc11bxx
9RO
((RW))
NA0Maximum Link Width Bit 5LKMLW_5vcc0xx
8RO
((RW))
NA0Maximum Link Width Bit 4LKMLW_4vcc0xx
7RO
((RW))
NA0Maximum Link Width Bit 3LKMLW_3vcc0xx
6RO
((RW))
NA1bMaximum Link Width Bit 2LKMLW_2vcc1bxx
5RO
((RW))
NA0Maximum Link Width Bit 1LKMLW_1vccxxx
4RO
((RW))
NA0Maximum Link Width Bit 0LKMLW_0vccxxx
3RO
((RW))
NA0Max Link Speed Bit 3
Max Link Speeds – This field indicates the supported maximum Link speed(s) of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.
Defined encodings are:
0001b: Supported Link Speeds Vector field bit 0.
0010b: Supported Link Speeds Vector field bit 1.
0011b: Supported Link Speeds Vector field bit 2.
0100b: Supported Link Speeds Vector field bit 3.
0101b: Supported Link Speeds Vector field bit 4.
0110b: Supported Link Speeds Vector field bit 5.
0111b: Supported Link Speeds Vector field bit 6.
LKMAXLS_ 3vcc0xx
2RO
((RW))
NA0Max Link Speed Bit 2 LKMAXLS_ 2vcc0xx
1RO
((RW))
NA0bMax Link Speed Bit 1LKMAXLS_ 1vcc0bxx
0RO
((RW))
NA1bMax Link Speed Bit 0LKMAXLS_ 0vcc1bxx
Offset Address: 51-50h (D0F0(D0F2)
Link Control 1Default Value: 0040h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:12RONA0Reservedrsv_32vccRxx
11RWNA0Enable Link Autonomous Bandwidth Interrupt
0: Disable.
1: Enable the generation of an interrupt to indicate that the autonomous bandwidth status bit (Rx53[7] (RLATNMBW) ) has been set.
((For internal verify reference: @((#TOGGLE=1)) ))
RLABITENvcc0xx
10RWNA0Enable Link Bandwidth Management Interrupt
0: Disable.
1: Enable the generation of an interrupt to indicate that the link bandwidth management status bit (Rx53[6] (RLBWMNGT) ) has been set.
((For internal verify reference: @((#TOGGLE=1)) ))
RLBMITENvcc0xx
9RWNA0Hardware Autonomous Width Control
0: Hardware can change the link width because of correcting unreliable link operations or power saving issue.
1: Hardware can change the link width only because of correcting unreliable link operations.
RHATNMWDvcc0x0
8RONA0Enable Clock Power Management
0: Disable1: Enable
RLCOCPMENvcc0xx
7RWNA0Extended Synch
0: FCU timer limit is 30us.
No. of FTS ordered set to be transmitted from L0s to L0 is N_FTS.
No. of TS1 to be transmitted in Recovery.RcvrLock is not limited.
1: FCU timer limit is 120us.
No. of FTS ordered set to be transmitted from L0s to L0 is 4096.
No. of TS1 to be transmitted in Recovery.RcvrLock is at least 1024.
LCESvcc00x
6RWNA1bCommon Clock Configuration
0: Indicates that this port and the component on the opposite end of the link are operating with asynchronous reference clock.
1: Indicates that this port and the component on the opposite end of the link are operating with a distributed common reference clock.
LCCCCvccxxx
5RONA0Retrain Link
Link retrain is initiated by writing 1 to this bit. This will direct the Physical Layer LTSSM to the Recovery state. Hardware will clear this bit to 0 when complete.
LCRLvcc0xx
4RWNA0Link Disable
0: Enable the link1: Disable the link
LCLDvcc0xx
3RO
((RW))
NA0Read Completion Boundary
0: 64 bytes1: 128 bytes
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
LCRCBvcc0xx
2RONA0Reservedrsv_33vccRxx
1:0RWNA00bLink Active State PM (ASPM) Control
00: Disable
01: Enable L0s entry
10: Enable L1 entry
11: Enable L0s and L1 entry
LCAPMS_ vcc00b00b00b
Offset Address: 53-52h (D0F0(D0F2)
Link Status 1Default Value: 1000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15RONA0Link Autonomous Bandwidth Status
This bit is set to 1b to indicate that hardware has autonomously changed link speed or width, without the port transitioning through DL_Down status, for reasons other than attempt to correct unreliable link operation.
*RLATNMBWvcc0xx
14RONA0Link Bandwidth Management Status
This bit is asserted when:
  1. LTSSM transits from Recovery to L0.
  2. Link speed is changed.
  3. Link width is changed.
RLBWMNGTvcc0xx
13RONA0Data Link Layer Link Active
0: Inactive1: Active
*DL_ACTIVEvccxxx
12RO
((RW))
NA1bSlot Clock Configuration
0: Use an independent clock irrespective of the presence of a reference on the connector.
1: Use the same physical reference clock that the platform provides on the connector.
((For Internal Reference: RO/RW through D0F5RxF0[0].))
LSSCCvccxxx
11RONA0Link Training
This bit indicate that Link training is in progress (Physical Layer LTSSM is in Configuration or Recovery state) or the Retrain Link bit is set but Link training has not yet begun. Hardware clears this bit once Link training is complete.
LSLTvcc0xx
10RONA0Training Error
Set when a Link training error occurs. Cleared by hardware upon successfully training of the Link to the L0 Link state.
LSTEvcc0xx
9RONA0Negotiated Link Width Bit 5
Hardwired to 0.
tbd_28vcc0xx
8:4RO((RW))NA0Negotiated Link Width Bits[4:0]
Default value set by hardware initial.
00001: x100010: x2
00100: x401000: x8
01000: x16
Others: Reserved
LSNLW_ vcc0xx
3:0RO((RW))NA0Current Link Speed
Current Link Speed – This field indicates the negotiated Link speed of the given PCI Express Link.
The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.
Defined encodings are:
0001: Supported Link Speeds Vector field bit 0.
0010: Supported Link Speeds Vector field bit 1.
0011: Supported Link Speeds Vector field bit 2.
0100: Supported Link Speeds Vector field bit 3.
0101: Supported Link Speeds Vector field bit 4.
0110: Supported Link Speeds Vector field bit 5.
0111: Supported Link Speeds Vector field bit 6.
All other encodings are Reserved.
The value in this field is undefined when the Link is not up.
LSLS_ vcc0xx
Offset Address: 57-54h (D0F0(D0F2)
Slot Capabilities 1Default Value: 0000 0020h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:19RO
((RW))
NA0Physical Slot Number; Reserved
Physical slot number attached to the port.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
SLPSN_ vcc0xx
18RO
((RW))
NA0No Command Completed Support
0: Not supported1: Supported
((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))
RSCANCCSvcc0xx
17RO
((RW))
NA0Electromechanical Interlock Present
0: Not present1: Present
((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))
RSCAEMIPvcc0xx
16:15RO
((RW))
NA00bSlot Power Limit Scale
Specify the scale used for the Slot Power Limit Value.
Range of values:
00: 1.0x01: 0.1x
10: 0.01x11: 0.001x
This register must be implemented if the Slot Implemented bit is set.
((For Internal Reference: Write to the field causes the Port to send the Set_Slot_Power_Limit message. RO/RW through D0F5 RxF0[0].))
RSPLS_ vcc0xx
14:7RO
((RW))
NA0Slot Power Limit Value
In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot.
This register must be implemented if the Slot Implemented bit is set.
((For Internal Reference: Write to the field causes the Port to send the Set_Slot_Power_Limit message. RO/RW through D0F5 RxF0[0].))
RSPLV_ vcc0xx
6RO
((RW))
NA0Hot-Plug Capable
1b indicates that this slot is capable of supporting hot-plug operations.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
((For internal verify reference: @((#TOGGLE=1)) ))
SCHP_CAPvcc0xx
5RO
((RW))
NA1bHot-Plug Surprise
1b indicates that an adapter present in this slot may be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow such removal without impact on successive software operation.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
((For internal verify reference: @((#TOGGLE=1)) ))
SCHPSvcc1xx
4RO
((RW))
NA0Power Indicator Present
When set to 1b, this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
((For internal verify reference: @((#TOGGLE=1)) ))
SCPIPvcc0xx
3RO
((RW))
NA0Attention Indicator Present
When set to 1b, this bit indicates that an Attention Indicator is electrically controlled by the chassis.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
((For internal verify reference: @((#TOGGLE=1)) ))
SCAIPvcc0xx
2RONA0MRL Sensor Present
Reserved
rsv_36vcc0xx
1RONA0Power Controller Present
Reserved
rsv_37vcc0xx
0RO
((RW))
NA0Attention Button Present
When set to 1b, this bit indicates that an Attention Button for this slot is electrically controlled by the chassis.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
((For internal verify reference: @((#TOGGLE=1)) ))
SCABPvcc0xx
Offset Address: 59-58h (D0F0(D0F2)
Slot Control 1Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:13RONA0Reservedrsv_39vccRxx
12RWNA0Enable Data Link Layer State Change
0: Disable1: Enable
If the Data Link Layer Link Active capability is implemented, when set to 1b, this field enables software notification when Data Link Layer Link Active field is changed.
((For internal verify reference: @((#TOGGLE=1)) ))
RDLSCHGENvcc0xx
11RONA0Electromechanical Interlock Control
0: Disable1: Enable
RSCOEMICvcc0xx
10RWNA0Power Controller Control
0: Power on1: Power off
If a power controller is implemented, this bit when written sets the power state of the slot per the defined encodings.
If the Power Controller Implemented field in the Slot Capabilities register is set to 0b, then writes to this field have no effect and the read value of this field is undefined.
SCPCCvcc0xx
9:8RO/RWNA00bPower Indicator Control
If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state.
Reads of this field must reflect the value from the latest write,even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined.
Defined encodings are:
00: Reserved01: On
10: Blink11: Off
This bit is RW when D0F02 Rx54[4] is set to 1.
Note: The default value of this field must be one of the non-Reserved values.
@((guardbit = SCPIP D0F02 RX54[4]))
((For Internal Reference:
00: Reserved01: On
10: Blink11: Off
Writes to this field cause the port to send the appropriate POWER_INDICATOR_* Message.))
SCPIC_ vcc0xx
7:6RO/RWNA00bAttention Indicator Control
If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined.
Defined encodings are:
00: Reserved01: On
10: Blink11: Off
This bit is RW when D0F02 Rx54[3] is set to 1.
Note: The default value of this field must be one of the non-Reserved values.
@((guardbit = SCAIP D0F20 RX54[3]))
((For Internal Reference:
00: Reserved01: On
10: Blink11: Off
Writes to this field cause the ort to send the appropriate ATTENTION_INDICATOR_* Message.))
SCAIC_ vcc0xx
5RO/RWNA0Enable Hot-Plug Interrupt
0: If the Hot Plug Capable field in the Slot Capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b.
1: When set to 1b, this bit enables generation of an interrupt on enabled hot-plug events.
This bit is RW when D0F02 Rx54[6] is set to 1.
@((guardbit = SCHP_CAP D0F02 RX54[6]))
((For Internal Reference:
0: Disable1: Enable
his bit when set enables generation of Hot-Plug interrupt on enabled Hot-Plug events.))
SCHPIEvcc0xx
4RWNA0Enable Command Completed Interrupt
0: If Command Completed notification is not supported, this bit must be hardwired to 0b.
1: When set to 1b, this bit enables software notification when a hot-plug command is completed by the Hot-Plug Controller.
((For Internal Reference:
0: Disable1: Enable
This bit when set enables the generation of Hot-Plug interrupt when a command is completed by the Hot-Plug controller.))
SCCCIEvcc0xx
3RWNA0Enable Presence Detect Change
When set to 1b, this bit enables software notification on a presence detect changed event.
((For Internal Reference:
0: Disable1: Enable
This bit when set enables the generation of Hot-Plug interrupt or WakeuPEvent on a presence detect changed event.))
SCPDCEvcc0xx
2RONA0Enable MRL Sensor Change
Reserved
((For Internal Reference:
0: Disable1: Enable ))
rsv_40vcc0xx
1RONA0Enable Power Fault Detected
Reserved
((For Internal Reference:
0: Disable1: Enable ))
rsv_41vcc0xx
0RO/RWNA0Enable Attention Button Pressed
When set to 1b, this bit enables software notification on an attention button pressed event. This bit is RW when D0F02 Rx54[0] is set to 1.
((For Internal Reference:
0: Disable1: Enable
This bit when set enables the generation of Hot-Plug interrupt or WakeuPEvent on an Attention Button pressed event.))
@((guardbit = SCABP D0F02 Rx54[0]))
SCABPEvcc0xx
Offset Address: 5B-5Ah (D0F0(D0F2)
Slot Status 1Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:9RONA0Reservedrsv_42vccRxx
8RONA0Data Link Layer State Changed
0: No state changed1: State changed
RDLSCHGvcc0xx
7RONA0Electromechanical Interlock StatusRSSEMISvcc0xx
6RONA0Presence Detect State
0: Slot empty
1: Card present in slot
SPDCSTvcc0xx
5RONA0MRL (Manually Operated Retention Latch) Sensor State
Reserved
rsv_43vcc0xx
4RONA0Command Completed
0: Not completed1: Completed
SSCCvcc0xx
3RONA0Presence Detect Change
0: Not changed1: Changed
SPDCvcc0xx
2RONA0MRL Sensor Change
0: Not changed1: Changed
tbd_29vcc0xx
1RONA0Power Fault Detected
0: Not changed1: Changed
tbd_30vcc0xx
0RONA0Attention Button Pressed
0: No state changed1: State changed
SSABPvcc0xx
Offset Address: 5D-5Ch (D0F0(D0F2)
Root ControlDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:5RONA0ReservedRsv_5c_5vccRxx
4RWNA0Enable CRS Software Visibility
0: Disable.
1: Enable the root port to return Configuration Request Retry Status (CRS) completion status to software.
((For internal verify reference: @((#TOGGLE=1)) ))
RCCRSSVEvcc0xx
3RWNA0Enable PME Interrupt
0: Disable.
1: Enable interrupt generation upon receipt of a PME message as reflected in the PME status register bit. A PME interrupt is also generated if the PME status register bit is set when this bit is set from a cleared state.
RCPMEIEvcc0xx
2RWNA0Enable System Error on Fatal Error
0: Disable.
1: Enable generation of a System Error if a Fatal Error (ERR_FATAL) is reported by any of the devices in the hierarchy associated with the root port, or by the root Port itself.
RCSEFEEvcc0xx
1RWNA0Enable System Error on Non-Fatal Error
0: Disable.
1: Enable generation of a System Error if a Non-Fatal Error (ERR_NONFATAL) is reported by any of the devices in the hierarchy associated with the root port, or by the root port itself.
RCSENFEEvcc0xx
0RWNA0Enable System Error on Correctable Error
0: Disable.
1: Enable generation of a System Error if a Correctable Error (ERR_COR) is reported by any of the devices in the hierarchy associated with the root port, or by the root port itself.
RCSECEEvcc0xx
Offset Address: 5F-5Eh (D0F0(D0F2)
Root CapabilitiesDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:1RONA0Reservedrsv_44_5evccRxx
0RO
((RW))
NA0Configuration Request Retry Status (CRS) Software Visibility
0: Disable. The Root Port cannot return CRS completion status to software.
1: Enable. The Root Port will return CRS completion status to software.
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
((For internal verify reference: @((#TOGGLE=1)) ))
RSCRSSFVvcc0xx
Offset Address: 63-60h (D0F0(D0F2)
Root StatusDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:18RONA0Reservedrsv_45vccRxx
17RONA0PME Pending
0: No pending PME.
1: Indicates another PME is pending when the PME Status (bit 16) is set.
RSPPvcc0xx
16RONA0PME Status
Indicates that the PME is asserted by the Requestor ID indicated in PME Requestor ID (bits[15:0]).
RSPSvcc0xx
15:0RONA0PME Requester ID
The Requestor ID of the last PME Requestor.
RSPRID_ vcc0xx
Offset Address: 67-64h (D0F0(D0F2)
Device Capabilities 2Default Value: 0000 0010h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:20RONA0ReservedRsv_64_6vccRxx
19:18RO
((RW))
NA0OBFF Supported
00: OBFF not supported.
01: OBFF supported using Message signaling only.
10: OBFF supported using WAKE# signaling only.
11: OBFF supported using WAKE# and Message signaling.
ROBFFSP_vcc0xx
17:12RONA0ReservedRsv_64_12vccRxx
11RO
((RW))
NA0LTR Mechanism Supported
A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism capability.
RLTRSPvcc0xx
10:6RONA0ReservedRsv_64_10vccxxx
5RO
((RW))
NA0Alternative Routing-ID Interpretation (ARI) Forwarding Supported
0: Not supported1: Supported
ARI is used to increase the number of functions supported by single device.
RARISPvcc0xx
4RO
((RW))
NA1bCompletion Timeout Disable Supported
0: Not support Completion Timeout Disable.
1: Support Completion Timeout Disable.
((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))
tbd_31vcc1xx
3:0RONA0Completion Timeout Ranges Supported
0: Not supported1: Supported
((For Internal Reference: The timeout value is in the range from 50us to 50ms, compliant with PCIe 1.1))
tbd_32vcc0xx
Offset Address: 69-68h (D0F0(D0F2)
Device Control 2Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15RONA0Reservedrsv_46vccRxx
14:13RWNA0OBFF Enable
00: Disabled
01: Enabled using Message signaling [Variation A]
10: Enabled using Message signaling [Variation B]
11: Enabled using WAKE# signaling
ROBFFEN_vcc0xx
12:11RONA0ReservedRsv_68_11vccRxx
10RWNA0LTR Mechanism Enable
When Set to 1b, this bit enables the Latency Tolerance Reporting (LTR) mechanism
RLTRENvcc0xx
9:6RONA0ReservedRsv_68_6vccRxx
5RO/RWNA0Enable ARI Forwarding
0: Disable. Check device number being 0 when turning downstream Type1 configuration to Type 0 configuration.
1: Enable. Never check device number when turning downstream Type1 configuration to Type 0 configuration.
This bit is RW when D0F02 Rx64[5] is set to 1.
((For Internal Reference: Internal design guideline
Default value of this bit is 0b. Must be hardwired to 0b if the ARI Forwarding Supported bit (D0F0(D0F2 Rx64[5]) is 0b.))
@((guardbit=RARISP D0F02 RX64[5]))
RARIENvcc0xx
4RWNA0Completion Timeout Disable Control
0: Enable completion timeout function.
1: Disable completion timeout function.
*RDISCPLTMvcc00x
3:0RONA0Completion Timeout Value
((For Internal Reference: Not support completion timeout programmability then hardwire this field to 0000b.))
tbd_33vcc0xx
Offset Address: 6B-6Ah (D0F0(D0F2)
Device Status 2Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:0RONA0Reservedrsv_47vccRxx
Offset Address: 6F-6Ch (D0F0(D0F2)
Link Capabilities 2Default Value: 0001 0202h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:19RONA0Reservedrsv_6c_31vccRxx
18RO
((RW))
NA0Lower SKP OS Reception Supported Speeds Vector
If this field is non-zero, it indicates that the Port, when operating at the indicated speed(s) supports SRIS and also supports receiving SKP OS at the rate defined for SRNS while running in SRIS.
Bit definitions within this field are:
Bit 0: 2.5 GT/sBit 1: 5.0 GT/s
Bit 2: 8.0 GT/sBits 6:3: RsvdP
RLOW_SKP_REC_SUPPORT_2vccxxX
17RO
((RW))
NA0Lower SKP OS Reception Supported Speeds VectorRLOW_SKP_REC_SUPPORT_1vccxxX
16RO
((RW))
NA1bLower SKP OS Reception Supported Speeds VectorRLOW_SKP_REC_SUPPORT_0vccxxX
15:12RONA0Reservedrsv_6c_15vccRxx
11RO
((RW))
NA0Lower SKP OS Generation Supported Speeds Vector
If this field is non-zero, it indicates that the Port, when operating at the indicated speed(s) supports SRIS and also supports software control of the SKP Ordered Set transmission scheduling rate.
Bit definitions within this field are:
Bit 0: 2.5 GT/sBit 1: 5.0 GT/s
Bit 2: 8.0 GT/s
RLOW_SKP_GEN_SUPPORT_2vccxxx
10RO
((RW))
NA0Lower SKP OS Generation Supported Speeds VectorRLOW_SKP_GEN_SUPPORT_1vccxxX
9RO
((RW))
NA1bLower SKP OS Generation Supported Speeds VectorRLOW_SKP_GEN_SUPPORT_0vccxxX
8RONA0CrossLink Supported
0 indicates the RP does not support CrossLink.
Rsv_6c_8vcc0xx
7RONA0Supported Link Speed Vector Bit 6
Reserved
LKMLS_ 6vcc0xx
6RONA0Supported Link Speed Vector Bit 5
Reserved
LKMLS_ 5vcc0xx
5RONA0Supported Link Speed Vector Bit 4
Reserved
LKMLS_ 4vcc0xx
4RONA0Supported Link Speed Vector Bit 3
Reserved
LKMLS_ 3vcc0xx
3RO
((RW))
NA0Supported Link Speed Vector Bit 2, 8.0GT/sLKMLS_2vcc0xx
2RO
((RW))
NA0Supported Link Speed Vector Bit 1, 5.0GT/sLKMLS_1vcc0bxx
1RO
((RW))
NA1bSupported Link Speed Vector Bit 0, 2.5 GT/sLKMLS_ 0vcc1bxx
0RONA0Reservedrsv_6c_0vccRxx
Offset Address: 71-70h (D0F0(D0F2)
Link Control 2Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:12RWNA0Compliance Preset / De-emphasis
For 8.0 GT/s Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
For 5.0 GT/s Data Rate: This bit field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
Defined Encodings are:
0001b: -3.5 dB
0000b: -6 dB
CMPPSDEEMPHS_vcc0xx
11RWNA0SKP Ordered Set (SOS) Transmission between Compliance Patterns
0: No SOS is sending between the (modified) compliance patterns.
1: The LTSSM is sending SOS periodically in between the (modified) compliance patterns.
RCMPSOSvcc0xx
10RWNA0Modified Compliance Pattern Set Bit
0: Device transmits normal compliance pattern if LTSSM enters Polling.Compliance state.
1: Device transmits modified compliance pattern if LTSSM enters Polling.Compliance state.
PMDCMPSETvcc0xx
9RWNA0Transmit Voltage Margin Setting
Bits [9:7]
000: Normal operating range.
001: 800-1200 mV for full swing and 400-700 mV for half-swing.
010 ~ (n-1): Values must be monotonic with a non-zero slope. The value of n must be greater than 3 and less than 7. At least two of these must be below the normal operating range of n: 200-400 mV for full-swing and 100-200 mV for half-swing.
n ~ 111: Reserved.
TXMGN _2vcc0xx
8RWNA0Transmit Voltage Margin Setting
Bits [9:7]
000: Normal operating range.
001: 800-1200 mV for full swing and 400-700 mV for half-swing.
010 ~ (n-1): Values must be monotonic with a non-zero slope. The value of n must be greater than 3 and less than 7. At least two of these must be below the normal operating range of n: 200-400 mV for full-swing and 100-200 mV for half-swing.
n ~ 111: Reserved.
TXMGN_1vcc0xx
7RWNA0Transmit Voltage Margin Setting
Bits [9:7]
000: Normal operating range.
001: 800-1200 mV for full swing and 400-700 mV for half-swing.
010 ~ (n-1): Values must be monotonic with a non-zero slope. The value of n must be greater than 3 and less than 7. At least two of these must be below the normal operating range of n: 200-400 mV for full-swing and 100-200 mV for half-swing.
n ~ 111: Reserved.
TXMGN_0vcc0xx
6RO
((RW))
NA0Selectable De-emphasis
0: -6 db1: -3.5db
When the link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an upstream component.
SELDEEMPHSvcc0xx
5RWNA0Disable Hardware Autonomous Speed
0: Enable hardware autonomous speed negotiation.
1: Disable hardware autonomous speed negotiation.
RHATNMSDvcc0x0
4RWNA0Enter Compliance
0: Normal negotiation.
1: Force to polling.compliance.
PCMPSETvcc0xx
3RWNA0Target Link Speed Bit 3LKTGLS_3 vcc000
2RWNA0Target Link Speed Bit 2LKTGLS_ 2vcc000
1RWNA0Target Link Speed Bit 1LKTGLS_ 1vcc000
0RWNA0Target Link Speed Bit 0LKTGLS_ 0vcc000
Offset Address: 73-72h (D0F0(D0F2)
Link Status 2Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:6RONA0Reservedrsv_49vccRxx
5RONA0Request the Link Equalization Process
This bit is Set to 1 by hardware to request the Link equalization process to be performed on the Link.
EQREQvccxxx
4RONA0Transmitter Equalization Procedure Completed -Phase 3
1: Phase 3 of the Transmitter Equalization procedure has successfully completed.
EQCOMPLE3vccxxx
3RONA0Transmitter Equalization Procedure Completed -Phase 2
1: Phase 2 of the Transmitter Equalization procedure has successfully completed.
EQCOMPLE2vccxxx
2RONA0Transmitter Equalization Procedure Completed -Phase 1
1: Phase 1 of the Transmitter Equalization procedure has successfully completed.
EQCOMPLE1vccxxx
1RONA0Transmitter Equalization Procedure Completed
1: Transmitter Equalization procedure has completed.
EQCOMPLEvccxxx
0RONA0Current Link De-emphasis Level
0: -6 db1: -3.5db
CURDEEMPHSvccxxx
Offset Address: 74-7Fh (D0F0(D0F2) – Reserved

Reserved for PCIe Slot Capabilities 2, Slot Control 2 and Slot Status 2 Register

Reserved for PCI Power Management Capability Structure Registers (80-87h)

Offset Address: 83-80h (D0F0(D0F2)
Power Management CapabilitiesDefault Value: C822 0001h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:27RO
((RW))
NA11001bPME Support
0: Not supported1: Supported
Bit 31, 30 and 27 are set to 1b (PME Message will be forwarded).
((For Internal Reference: RW when D0F5 RxF0[0]=1.))
PMCPME_ vcc19hxx
26RO
((RW))
NA0D2 Support
0: Not supported1: Supported
((For Internal Reference: RW when D0F5 RxF0[0]=1.))
PMCD2Svcc0xx
25RO
((RW))
NA0D1 Support
0: Not supported1: Supported
((For Internal Reference: RW when D0F5 RxF0[0]=1.))
PMCD1Svcc0xx
24:22RO
((RW))
NA0AUX Current
((For Internal Reference: This bit will be write-able when D0F5 RxF0[0] is programmed to 1.))
PMCAUXC_ vcc0xx
21RO
((RW))
NA1bDevice Specific Initialization
Do not program.
((For Internal Reference: RW when D0F5 RxF0[0]=1.))
PMCDSIvcc1xx
20:19RONA0Reservedrsv_53vccRxx
18:16RONA010bVersiontbd_34vcc010bxx
15:8RO((RW))NA00hNext Capability Pointertbd_35vcc00hxx
7:0RONA01hCapability ID
01h indicates extended capability ID for the advanced error reporting capability.
tbd_36vcc01hxx
Offset Address: 87-84h (D0F0(D0F2)
Power Management Status / ControlDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:24RONA0Power Management Datatbd_37vccRxx
23RO
((RW))
NA0Enable Bus Power / Clock Control
0: Disable1: Enable
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
tbd_38vccxxx
22RO
((RW))
NA0B2 / B3 Support
((For Internal Reference: RO/RW through D0F5 RxF0[0].))
tbd_39vccxxx
21:16RONA0Reservedrsv_54vccRxx
15RONA0PME Status
This bit’s setting is not modified by hot, warm or cold reset.
PMESDvcc0xx
14:13RONA0Data Scaletbd_40vcc0xx
12:9RONA0Data Selecttbd_41vcc0xx
8RWNA0PME Enable
0: Disable1: Enable
This bit’s setting is not modified by hot, warm or cold reset.
((For internal verify reference: @((#TOGGLE=1)) ))
PMEENvcc0xx
7:2RONA0Reservedrsv_55vccRxx
1:0RWNA00bPower State
00: D001: D1
10: D211: D3 hot
PWSD_ vcc0xx

Reserved Registers (88-8Fh)

Offset Address: 8B-88h (D0F0(D0F2)
Reserved ((Internal-RW))Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RWNA0Reserved
((Writing 1 or 0 to these bits does not change any behavior of this chip.))
Rx88[31:0]vcc0xx
Offset Address: 8F-8Ch (D0F0(D0F2)
Reserved ((Internal-RW))Default Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:0RWNA0Reserved
((Writing 1 or 0 to these bits does not change any behavior of this chip.))
Rx8C[31:0]vcc0xx


@((REG_GROUP (System SVADDVAD Control): RANGE=(90h,3FFh)))

System View Address Decode (90-3FFh)

SVADLimit = highest SVAD limit address

B4GMMIOBase = min(MMIOB2G,MMIO2T4G)

MMIOB2G Decode (90-B7h)

Offset Address: 93-90h (D0F2)
MMIOCFG decoderDefault Value: 0nnn nn
00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0RDID_RID_LOCK_D0F2
((For Internal Reference: DID_RID_lock_bit
0: DeviceID, RevisionID and RDID_RID_LOCK_D0F2 is RW;
1: DeviceID, RevisionID and RDID_RID_LOCK_D0F2 is RO;
@((#control_lock = lock_port RDID_RID_LOCK_D0F2))
 ))
RDID_RID_LOCK_D0F2vcc0xx
30RWLRO0RSVAD_LOCK
This is a lock bit for the related register “SVAD”:
1: When this ((Lock_bit)) is set to 1, the SVAD related register is RO.
0: When this ((Lock_bit)) is set to 0, the SVAD related regisrer is RW
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK))
@((#control_txt_lock = LOCK_SMRAM)) 
@((#control_txt_unlock = UNLOCK_SMRAM)) 
 ))
((For Internal Reference: @((#USER=HIF))  ))
RSVAD_LOCKvccxxx
29RWLRO0RVID_DID_LOCK_D0F2
((For Internal Reference: VID_DID_lock_bit
0: VendorID and RVID_DID_LOCK_D0F2 is RW;
1: VendorID and RVID_DID_LOCK_D0F2 is RO;
@((#control_lock = lock_port RVID_DID_LOCK_D0F2))
@((#control_default = NB_VID_DID_LOCK))
))
RVID_DID_LOCK_D0F2vccxxx
28RWLRO0C2M_Tseg_range _LOCK_D0F2
0: C2M Tseg range control is RW;
1: C2M Tseg range Protection control  is RO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0.
@((#control_lock=lock_port RSVAD_TSEG
LOCK )) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_TSEGLOCKvccxxx
27:8RWLROROMSIPMMIOCFG base
This 20 bits are MMIOCFG base address
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[59:40]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFGBASE[45:26]vccxxx
7:3RONA0Reserved Rx90[7:3]vccRxx
2RWLRO0RCLASS_CODE_LOCK_D0F2
((For Internal Reference: ClassCode_lock_bit
0: ClassCode and RCLASS_CODE_LOCK_D0F2 is RW;
1: ClassCode and RCLASS_CODE_LOCK_D0F2 is RO;
@((#control_lock = lock_port RCLASS_CODE_LOCK_D0F2))
 ))
RCLASS_CODE_LOCK_D0F2vccxxx
1RWLRO0C2M_CDEFseg_range_LOCK_D0F2
0: C2M CDEFGseg range control is RW;
1: C2M CDEFseg range Protection control  is RO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock=lock_port RSVAD_CDEFSEG
LOCK )) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_CDEFSEGLOCKvccxxx
0RONA0Reserved Rx90[0]vccRxx
Offset Address: 97-94h (D0F2)
MMIOCFG limit addressDefault Value:nnnn nnnnh
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:29RONA0Reserved Rx94[31:29]vccRxx
28:24RWLROROMSIPMMIOCFG SN3 bus number limit
This 5 bits are sub node3 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[24:20]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N3_LIMIT [27:23]vccxxx
23:21RONA0Reserved Rx94[23:21]vccRxx
20:16RWLROROMSIPMMIOCFG SN2 bus number limit
This 5 bits are sub node2 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[29:25]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N2_LIMIT [27:23]vccxxx
15:13RONA0Reserved Rx94[15:13]vccRxx
12:8RWLROROMSIPMMIOCFG SN1 bus number limit
This 5 bits are sub node1 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[34:30]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N1_LIMIT[27:23]vccxxx
7:5RONA0Reserved Rx94[7:5]vccRxx
4:0RWLROROMSIPMMIOCFG SN0 bus number limit
This 5 bits are sub node0 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[39:35])) ((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N0_LIMIT[27:23]vccxxx
Offset Address: 9B-98h (D0F2)
MMIOCFG limit addressDefault Value: nnnn nnnnh
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:29RONA0Reserved Rx98[31:29]vccRxx
28:24RWLROROMSIPMMIOCFG SN7 bus number limit
This 5 bits are sub node7 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[4:0]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N7_LIMIT [27:23]vccxxx
23:21RONA0Reserved Rx98[23:21]vccRxx
20:16RWLROROMSIPMMIOCFG SN6 bus number limit
This 5 bits are sub node6 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[9:5]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N6_LIMIT [27:23]vccxxx
15:13RONA0Reserved Rx98[15:13]vccRxx
12:8RWLROROMSIPMMIOCFG SN5 bus number limit
This 5 bits are sub node5 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[14:10]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N5_LIMIT[27:23]vccxxx
7:5RONA0Reserved Rx98[7:5]vccRxx
4:0RWLROROMSIPMMIOCFG SN4 bus number limit
This 5 bits are sub node4 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP1, HW_DATA = ROMSIP_VKCFG_DATA[19:15]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N4_LIMIT[27:23]vccxxx
Offset Address: 9F-9Ch (D0F2)
MMIOCFG limit addressDefault Value: nnnn
nnnnh
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:29RONA0Reserved Rx9C[31:29]vccRxx
28:24RWLROROMSIPMMIOCFG SN11 bus number limit
This 5 bits are sub node11 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[48:44]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N11_LIMIT [27:23]vccxxx
23:21RONA0Reserved Rx9C[23:21]vccRxx
20:16RWLROROMSIPMMIOCFG SN10 bus number limit
This 5 bits are sub node10 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[53:49]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N10_LIMIT [27:23]vccxxx
15:13RONA0Reserved Rx9C[15:13]vccRxx
12:8RWLROROMSIPMMIOCFG SN9 bus number limit
This 5 bits are sub node9 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[58:54]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N9_LIMIT[27:23]vccxxx
7:5RONA0Reserved Rx9C[7:5]vccRxx
4:0RWLROROMSIPMMIOCFG SN8 bus number limit
This 5 bits are sub node8 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[63:59]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N8_LIMIT[27:23]vccxxx
Offset Address: A3-A0h (D0F2)
MMIOCFG limit addressDefault Value: nnnn
nnnnh
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:29RONA0Reserved RxA0[31:29]vccRxx
28:24RWLROROMSIPMMIOCFG SN15 bus number limit
This 5 bits are sub node15 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[28:24]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N15_LIMIT [27:23]vccxxx
23:21RONA0Reserved RxA0[23:21]vccRxx
20:16RWLROROMSIPMMIOCFG SN14 bus number limit
This 5 bits are sub node14 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[33:29]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N14_LIMIT [27:23]vccxxx
15:13RONA0Reserved RxA0[15:13]vccRxx
12:8RWLROROMSIPMMIOCFG SN13 bus number limit
This 5 bits are sub node13 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[38:34]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N13_LIMIT[27:23]vccxxx
7:5RONA0Reserved RxA0[7:5]vccRxx
4:0RWLROROMSIPMMIOCFG SN12 bus number limit
This 5 bits are sub node12 MMIOCFG bus number limit.
((For Internal ROMSIP handling: HW_EN = SELSIP2, HW_DATA = ROMSIP_VKCFG_DATA[43:39]))
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOCFG_N12_LIMIT[27:23]vccxxx
Offset Address: A7-A4h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:4RONA0Reserved RxA4[31:4]vccRxx
3:1RWLRO0MMIO Below 2G (MMIOB2G) base address
MMIOB2G base address, A[39:32] are fixed to 0, A[31] is fixed to 0, A[30:28] are programmable, A[27:0] are fixed to 0.
MMIOB2G Limit address is fixed to 2G-1, when MMIOB2G is valid, any address X hit MMIOB2G range( MMIOB2G_base <= X <=MMIOB2G_Limit) is claimed by MMIO decoder.
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock=lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GBASE[30:28]vccxxx
0RWLRO0MMIO Below 2G disable
1: MMIO Below 2G is invalid
0: MMIO Below 2G is valid
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2G_DISvccxxx
Offset Address: AB-A8h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO Below 2G (MMIOB2G) entry7 target node
A[30:26]==5’d7: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ7[3:0]vccxxx
27:24RWLRO0MMIO Below 2G (MMIOB2G) entry6 target node
A[30:26]==5’d6: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ6[3:0]vccxxx
23:20RWLRO0MMIO Below 2G (MMIOB2G) entry5 target node
A[30:26]==5’d5: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ5[3:0]vccxxx
19:16RWLRO0MMIO Below 2G (MMIOB2G) entry4 target node
A[30:26]==5’d4: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ4[3:0]vccxxx
15:12RWLRO0MMIO Below 2G (MMIOB2G) entry3 target node
A[30:26]==5’d3: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ3[3:0]vccxxx
11:8RWLRO0MMIO Below 2G (MMIOB2G) entry2 target node
A[30:26]==5’d2: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ2[3:0]vccxxx
7:4RWLRO0MMIO Below 2G (MMIOB2G) entry1 target node
A[30:26]==5’d1: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ1[3:0]vccxxx
3:0RWLRO0MMIO Below 2G (MMIOB2G) entry0 target node
A[30:26]==5’d0: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ0[3:0]vccxxx
Offset Address: AF-ACh (D0F2)
MMIOB2G decoderDefault Value:0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO Below 2G (MMIOB2G) entry15 target node
A[30:26]==5’d15: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ15[3:0]vccxxx
27:24RWLRO0MMIO Below 2G (MMIOB2G) entry14 target node
A[30:26]==5’d14: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ14[3:0]vccxxx
23:20RWLRO0MMIO Below 2G (MMIOB2G) entry13 target node
A[30:26]==5’d13: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ13[3:0]vccxxx
19:16RWLRO0MMIO Below 2G (MMIOB2G) entry12 target node
A[30:26]==5’d12: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ12[3:0]vccxxx
15:12RWLRO0MMIO Below 2G (MMIOB2G) entry11 target node
A[30:26]==5’d11: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ11[3:0]vccxxx
11:8RWLRO0MMIO Below 2G (MMIOB2G) entry10 target node
A[30:26]==5’d10: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ10[3:0]vccxxx
7:4RWLRO0MMIO Below 2G (MMIOB2G) entry9 target node
A[30:26]==5’d9: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ9[3:0]vccxxx
3:0RWLRO0MMIO Below 2G (MMIOB2G) entry8 target node
A[30:26]==5’d8: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ8[3:0]vccxxx
Offset Address: B3-B0h (D0F2)
MMIOB2G decoder Default Value:0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO Below 2G (MMIOB2G) entry23 target node
A[30:26]==5’d23: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ23[3:0]vccxxx
27:24RWLRO0MMIO Below 2G (MMIOB2G) entry22 target node
A[30:26]==5’d22: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ22[3:0]vccxxx
23:20RWLRO0MMIO Below 2G (MMIOB2G) entry21 target node
A[30:26]==5’d21: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ21[3:0]vccxxx
19:16RWLRO0MMIO Below 2G (MMIOB2G) entry20 target node
A[30:26]==5’d20: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ20[3:0]vccxxx
15:12RWLRO0MMIO Below 2G (MMIOB2G) entry19 target node
A[30:26]==5’d19: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ19[3:0]vccxxx
11:8RWLRO0MMIO Below 2G (MMIOB2G) entry18 target node
A[30:26]==5’d18: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ18[3:0]vccxxx
7:4RWLRO0MMIO Below 2G (MMIOB2G) entry17 target node
A[30:26]==5’d17: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ17[3:0]vccxxx
3:0RWLRO0MMIO Below 2G (MMIOB2G) entry16 target node
A[30:26]==5’d16: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ16[3:0]vccxxx
Offset Address: B7-B4h (D0F2)
MMIOB2G decoderDefault Value:0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO Below 2G (MMIOB2G) entry31 target node
A[30:26]==5’d31: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ31[3:0]vccxxx
27:24RWLRO0MMIO Below 2G (MMIOB2G) entry30 target node
A[30:26]==5’d30: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ30[3:0]vccxxx
23:20RWLRO0MMIO Below 2G (MMIOB2G) entry29 target node
A[30:26]==5’d29: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ29[3:0]vccxxx
19:16RWLRO0MMIO Below 2G (MMIOB2G) entry28 target node
A[30:26]==5’d28: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ28[3:0]vccxxx
15:12RWLRO0MMIO Below 2G (MMIOB2G) entry27 target node
A[30:26]==5’d27: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ27[3:0]vccxxx
11:8RWLRO0MMIO Below 2G (MMIOB2G) entry26 target node
A[30:26]==5’d26: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ26[3:0]vccxxx
7:4RWLRO0MMIO Below 2G (MMIOB2G) entry25 target node
A[30:26]==5’d25: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ25[3:0]vccxxx
3:0RWLRO0MMIO Below 2G (MMIOB2G) entry24 target node
A[30:26]==5’d24: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIOB2GTMVEQ24[3:0]vccxxx

MMIO2T4G Decode (B8-CBh)

Offset Address: BB-B8h (D0F2)
MMIO2T4G decoderDefault Value:0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:3RONA0ReservedRxB8[31:3]vccxxx
2:0RWLRO0MMIO 2 to 4G (MMIO2T4G) base address
MMIO2T4G base address, A[39:32] are fixed to 0, A[31] is fixed to 1, A[30:28] are programmable, A[27:0] are fixed to 0.
MMIO2T4G Limit address is fixed to 4G-1, any address X hit MMIO2T4G range( MMIO2T4G_base <= X <=MMIO2T4G_Limit) is claimed by MMIO decoder.
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock=lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GBASE[30:28]vccxxx
Offset Address: BF-BCh (D0F2)
MMIO2T4G decodeDefault Value:0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO 2 To 4G (MMIO2T4G) entry7 target node
A[30:26]==5’d7: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ7[3:0]vccxxx
27:24RWLRO0MMIO 2 To 4G (MMIO2T4G) entry6 target node
A[30:26]==5’d6: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ6[3:0]vccxxx
23:20RWLRO0MMIO 2 To 4G (MMIO2T4G) entry5 target node
A[30:26]==5’d5: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ5[3:0]vccxxx
19:16RWLRO0MMIO 2 To 4G (MMIO2T4G) entry4 target node
A[30:26]==5’d4: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ4[3:0]vccxxx
15:12RWLRO0MMIO 2 To 4G (MMIO2T4G) entry3 target node
A[30:26]==5’d3: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ3[3:0]vccxxx
11:8RWLRO0MMIO 2 To 4G (MMIO2T4G) entry2 target node
A[30:26]==5’d2: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ2[3:0]vccxxx
7:4RWLRO0MMIO 2 To 4G (MMIO2T4G) entry1 target node
A[30:26]==5’d1: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ1[3:0]vccxxx
3:0RWLRO0MMIO 2 To 4G (MMIO2T4G) entry0 target node
A[30:26]==5’d0: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ0[3:0]vccxxx
Offset Address: C3-C0h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO 2 To 4G (MMIO2T4G) entry15 target node
A[30:26]==5’d15: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ15[3:0]vccxxx
27:24RWLRO0MMIO 2 To 4G (MMIO2T4G) entry14 target node
A[30:26]==5’d14: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ14[3:0]vccxxx
23:20RWLRO0MMIO 2 To 4G (MMIO2T4G) entry13 target node
A[30:26]==5’d13: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ13[3:0]vccxxx
19:16RWLRO0MMIO 2 To 4G (MMIO2T4G) entry12 target node
A[30:26]==5’d12: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ12[3:0]vccxxx
15:12RWLRO0MMIO 2 To 4G (MMIO2T4G) entry11 target node
A[30:26]==5’d11: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ11[3:0]vccxxx
11:8RWLRO0MMIO 2 To 4G (MMIO2T4G) entry10 target node
A[30:26]==5’d10: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ10[3:0]vccxxx
7:4RWLRO0MMIO 2 To 4G (MMIO2T4G) entry9 target node
A[30:26]==5’d9: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ9[3:0]vccxxx
3:0RWLRO0MMIO 2 To 4G (MMIO2T4G) entry8 target node
A[30:26]==5’d8: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ8[3:0]vccxxx
Offset Address: C7-C4h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO 2 To 4G (MMIO2T4G) entry23 target node
A[30:26]==5’d23: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ23[3:0]vccxxx
27:24RWLRO0MMIO 2 To 4G (MMIO2T4G) entry22 target node
A[30:26]==5’d22: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ22[3:0]vccxxx
23:20RWLRO0MMIO 2 To 4G (MMIO2T4G) entry21 target node
A[30:26]==5’d21: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ21[3:0]vccxxx
19:16RWLRO0MMIO 2 To 4G (MMIO2T4G) entry20 target node
A[30:26]==5’d20: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ20[3:0]vccxxx
15:12RWLRO0MMIO 2 To 4G (MMIO2T4G) entry19 target node
A[30:26]==5’d19: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ19[3:0]vccxxx
11:8RWLRO0MMIO 2 To 4G (MMIO2T4G) entry18 target node
A[30:26]==5’d18: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ18[3:0]vccxxx
7:4RWLRO0MMIO 2 To 4G (MMIO2T4G) entry17 target node
A[30:26]==5’d17: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ17[3:0]vccxxx
3:0RWLRO0MMIO 2 To 4G (MMIO2T4G) entry16 target node
A[30:26]==5’d16: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ16[3:0]vccxxx
Offset Address: CB-C8h (D0F2)
MMIO2T4G decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MMIO 2 To 4G (MMIO2T4G) entry31 target node
A[30:26]==5’d31: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ31[3:0]vccxxx
27:24RWLRO0MMIO 2 To 4G (MMIO2T4G) entry30 target node
A[30:26]==5’d30: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ30[3:0]vccxxx
23:20RWLRO0MMIO 2 To 4G (MMIO2T4G) entry29 target node
A[30:26]==5’d29: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ29[3:0]vccxxx
19:16RWLRO0MMIO 2 To 4G (MMIO2T4G) entry28 target node
A[30:26]==5’d28: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ28[3:0]vccxxx
15:12RWLRO0MMIO 2 To 4G (MMIO2T4G) entry27 target node
A[30:26]==5’d27: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ27[3:0]vccxxx
11:8RWLRO0MMIO 2 To 4G (MMIO2T4G) entry26 target node
A[30:26]==5’d26: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ26[3:0]vccxxx
7:4RWLRO0MMIO 2 To 4G (MMIO2T4G) entry25 target node
A[30:26]==5’d25: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ25[3:0]vccxxx
3:0RWLRO0MMIO 2 To 4G (MMIO2T4G) entry24 target node
A[30:26]==5’d24: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_MMIO2T4GTMVEQ24[3:0]vccxxx

ABSEG (CC-D3h)

Offset Address: CF-CCh (D0F2)
ABSEGDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:8RONA0Reserved RxC8[31:8]vccRxx
7RWLNA0C2M Tseg range Protection control
When this bit set to 1 then C2M Tseg range protection is removed. This bit is valid only when RxCC[2,1] = [0,0], please reference table 1 for detail. Note: The DMA protection is always enabled, do not effect by this bit.
1: disable C2M Tseg range protection
0: enable C2M Tseg range protection
Please reference table 1
((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0.
@((#control_lock = lock_port RSVAD_TSEGLOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_TSEGPRTDISvccxxx
6:3RWLRO0A/B SEG(VGA memory) decode for target to MMIO  - for memory address range in A0000h to BFFFFh
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ABSEG_MMIO_TGTvccxxx
2:1RWLRO0A/B & T SEG access control to system memory or MMIO
Reference
table1

((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ABSEG_SELvccxxx
0RONA0Reserved RxBC[0]vccRxx

table1

RxCC[2]RxCC[1]RxCC[7]Cycle
Type
Code Read
Target
Data Access
Target
000NormalMMIO *1MMIO *1
000SMMSystem Memory *2System Memory *2
001NormalA/B Seg ->MMIO *1
T Seg -> System Memory *3
A/B Seg ->MMIO *1
T Seg -> System Memory *3
001SMMSystem Memory *2System Memory *2
-1xNormal/SMMSystem Memory *2System Memory *2
10xNormalMMIO *1MMIO *1
10xSMMSystem Memory *2MMIO *1

Chipset base on the request from CPU is in normal/SMM mode and RxCC[2:1] to re-direct the cycle to MMIO or System memory.

Note 1: For target to MMIO and in A/B SEG range, chipset also reference RxCC[2:1] to re-direct the cycle to sub node. In Tseg range, chipset always forward the cycle to local sub node.

Note 2: For target to System Memory, chipset also reference SVAD entries to re-direct the cycle to master/slave socket.

Note 3: For target to System Memory in T seg range, it is used for CPU SMRR enable with WB cache mode only.

DMA protection:

Note 1: Chipset always protect A0000h~FFFFFh range. The DMA cycle issue by PCI or PCIE device target to this range then will be abored by Chipset: for write, discard the request and data; for read: give back all ‘1” data to device.

Note 2. When RTSMMEN = 1 then chipset protect the DMA cycle target to T SEG range.

-          T SEG range start from “RLOWTOPA – T SEG size(in SM_SIZE[1:0])” to “RLOWTOPA – 1”

Note 3. When Memory Hole enable then chipset forward the cycle to PCI.

Note 4. When DPR enable, then chipset protect the DMA cycle target to DPR range.

Offset Address: D3-D0h (D0F2)
C/D/E/F SEGDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0C/D/E/F SEG decode control when target to MMIO controlled by RxD0[25:0]
The value is the target sub node number;
This register control all C/D/E/F segment.
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
Note: when target to system memory, chipset base on SVAD to select to target socket.
RSVAD_CDEFSEG_MMIO_TGTvccxxx
27:26RONA0ReservedRxCC[27:26]vccxxx
25:24RWLRO0F0000-FFFFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENFF[1:0]vccxxx
23:22RWLRO0E0000-E3FFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENE0[1:0]vccxxx
21:20RWLRO0E4000-E7FFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENE4[1:0]vccxxx
19:18RWLRO0E8000-EBFFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENE8[1:0]vccxxx
17:16RWLRO0EC000-EFFFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENEC[1:0]vccxxx
15:14RWLRO0D0000-D3FFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SEND0[1:0]vccxxx
13:12RWLRO0D4000-D7FFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SEND4[1:0]vccxxx
11:10RWLRO0D8000-DBFFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SEND8[1:0]vccxxx
9:8RWLRO0DC000-DFFFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENDC[1:0]vccxxx
7:6RWLRO0C0000-C3FFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENC0[1:0]vccxxx
5:4RWLRO0C4000-C7FFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENC4[1:0]vccxxx
3:2RWLRO0C8000-CBFFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENC8[1:0]vccxxx
1:0RWLRO0CC000-CFFFFh Memory Space Access Control
00b: Read / Write disable;
01b: Write enable;
10b: Read enable;
11b: Read / Write enable
((For Internal Reference: This bit is RW when D0F2 Rx90 [1] is set to 0.
@((#control_lock = lock_port RSVAD_CDEFSEGLOCK)) ))
SENCC[1:0]vccxxx

MMIO VGA IO and Legacy IO Decode (D4-10Fh)

Offset Address: D7-D4h (D0F2)
MMIO and VGA IO decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:30RWLRO0Memory Hole
00: None
01: 512K ~ 640K
10: 15M ~ 16M (1M)
11: 14M ~ 16M (2M)
Limitation: always forward to master socket MMIO space(PCI) when hit memory hole range.
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RHOLE[1:0]vccxxx
29RWLRO0Top SM Memory Enable
This bit is the enable bit for the SM Memory at the top of the memory below 4G to be activated. When this bit is enabled, the memory with size defined by bits [1:0] will be deducted from the top of the system memory and be used for SM mode.
Top SM Memory range : B4GMemLimit(RLOWTOPA)+1 - SM_SIZE <= X <= B4GMemLimit
0: Disabled.1: Enabled.

((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0.
@((#control_lock = lock_port RSVAD_TSEGLOCK)) ))
RTSMMENvccxxx
28:27RWLRO0Top SM Memory Size
For SM mode, these two bits defined the size of the memory at the top of the memory below 4G. They are activated only when bit-2 is 1.
00: 4M.

01: 8M.
10: 16M.

11: 32M.
((For Internal Reference: This bit is RW when D0F2 Rx90 [28] is set to 0.
@((#control_lock = lock_port RSVAD_TSEGLOCK)) ))
SM_SIZE[1:0]vccxxx
26:5RONA0ReservedRxD0[26:5]vccRxx
4:1RWLRO0Legacy VGA IO target select – in IO range 3B0h-3BBh, 3C0h-3DFh
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_VGA_TGT[3:0]vccxxx
0RONA0ReservedRxD0[0]vccRxx
Offset Address: DB-D8h (D0F2)
legacy IO decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0Legacy IO entry7 target node
A[15:11]==5’d7: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT7[3:0]vccxxx
27:24RWLRO0Legacy IO entry6 target node
A[15:11]==5’d6: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT6[3:0]vccxxx
23:20RWLRO0Legacy IO entry5 target node
A[15:11]==5’d5: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT5[3:0]vccxxx
19:16RWLRO0Legacy IO entry4 target node
A[15:11]==5’d4: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT4[3:0]vccxxx
15:12RWLRO0Legacy IO entry3 target node
A[15:11]==5’d3: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT3[3:0]vccxxx
11:8RWLRO0Legacy IO entry2 target node
A[15:11]==5’d2: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT2[3:0]vccxxx
7:4RWLRO0Legacy IO entry1 target node
A[15:11]==5’d1: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT1[3:0]vccxxx
3:0RWLRO0Legacy IO entry0 target node
A[15:11]==5’d0: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT0[3:0]vccxxx
Offset Address: DF-DCh (D0F2)
legacy IO decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0Legacy IO entry15 target node
A[15:11]==5’d7: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT15[3:0]vccxxx
27:24RWLRO0Legacy IO entry14 target node
A[15:11]==5’d14: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT14[3:0]vccxxx
23:20RWLRO0Legacy IO entry13 target node
A[15:11]==5’d13: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT13[3:0]vccxxx
19:16RWLRO0Legacy IO entry12 target node
A[15:11]==5’d12: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT12[3:0]vccxxx
15:12RWLRO0Legacy IO entry11 target node
A[15:11]==5’d11: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT11[3:0]vccxxx
11:8RWLRO0Legacy IO entry10 target node
A[15:11]==5’d10: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT10[3:0]vccxxx
7:4RWLRO0Legacy IO entry9 target node
A[15:11]==5’d9: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT9[3:0]vccxxx
3:0RWLRO0Legacy IO entry8 target node
A[15:11]==5’d8: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT8[3:0]vccxxx
Offset Address: E3-E0h (D0F2)
legacy IO decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0Legacy IO entry23 target node
A[15:11]==5’d23: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT23[3:0]vccxxx
27:24RWLRO0Legacy IO entry22 target node
A[15:11]==5’d22: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT22[3:0]vccxxx
23:20RWLRO0Legacy IO entry21 target node
A[15:11]==5’d21: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT21[3:0]vccxxx
19:16RWLRO0Legacy IO entry20 target node
A[15:11]==5’d20: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT20[3:0]vccxxx
15:12RWLRO0Legacy IO entry19 target node
A[15:11]==5’d19: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT19[3:0]vccxxx
11:8RWLRO0Legacy IO entry18 target node
A[15:11]==5’d18: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT18[3:0]vccxxx
7:4RWLRO0Legacy IO entry17 target node
A[15:11]==5’d17: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT17[3:0]vccxxx
3:0RWLRO0Legacy IO entry16 target node
A[15:11]==5’d16: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT16[3:0]vccxxx
Offset Address: E7-E4h (D0F2)
legacy IO decoderDefault Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0Legacy IO entry31 target node
A[15:11]==5’d31: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT31[3:0]vccxxx
27:24RWLRO0Legacy IO entry30 target node
A[15:11]==5’d30: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT30[3:0]vccxxx
23:20RWLRO0Legacy IO entry29 target node
A[15:11]==5’d29: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT29[3:0]vccxxx
19:16RWLRO0Legacy IO entry28 target node
A[15:11]==5’d28: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT28[3:0]vccxxx
15:12RWLRO0Legacy IO entry27 target node
A[15:11]==5’d27: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT27[3:0]vccxxx
11:8RWLRO0Legacy IO entry26 target node
A[15:11]==5’d26: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT26[3:0]vccxxx
7:4RWLRO0Legacy IO entry25 target node
A[15:11]==5’d25: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT25[3:0]vccxxx
3:0RWLRO0Legacy IO entry24 target node
A[15:11]==5’d24: the request is routed to the node indicated by this register value
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_IO_TGT_SEL_ENT24[3:0]vccxxx
Offset Address: E9-E8h (D0F2)
Multi-die link readyDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:1RONA0ReservedRxE8[15:1]vccRxx
0RWLRO0This bit indicate all ZPI/OPI link of the platform initial done.
1 means ZPI/OPI link ready
0 means ZPI/OPI not ready
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
MULTI_DIE_ALL_LINK_READY vccxxx
Offset Address: EA-10Fh (D0F2) – Reserved

MEM ENTRY (110-34Fh)

Offset Address: 113-110h (D0F2)
MEM_ENT0Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry0 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry0 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry0 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry0 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry0 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry0 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry0 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry0 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST0[3:0]vccxxx
Offset Address: 117-114h (D0F2)
MEM_ENT0Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry0 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry0 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry0 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry0 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry0 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry0 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry0 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry0 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0TARGET _LIST8[3:0]vccxxx
Offset Address: 11B-118h (D0F2)
MEM_ENT0Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry0 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0ATTRvccxxx
30:13RWLRO3FFFFhMEM entry0 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0LADDR[45:28]vccxxx
12:11RWLRO0MEM entry0 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME0ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx118[11:0]vccxxx

Note1: The SVAD entry 0 base address = 0, SVAD entry 0 Limit address must not 0.

Note 2: For SVAD entry 1 to 47,  the SVAD entry N base address =  SVAD entry N-1 Limit address +1;  This SVAD entry is invalid if SVAD entry N Limit address = SVAD entry N-1 Limit address.

programming rule: Software should update Limit address from entry 47 to 0 to avoid some corner case cause decode fail.

Offset Address: 11F-11Ch (D0F2)
MEM_ENT1Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry1 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry1 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry1 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry1 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry1 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry1 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry1 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry1 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST0[3:0]vccxxx
Offset Address: 123-120h (D0F2)
MEM_ENT1Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry1 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry1 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry1 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry1 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry1 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry1 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry1 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry1 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1TARGET _LIST8[3:0]vccxxx
Offset Address: 127-124h (D0F2)
MEM_ENT1Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry1 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1ATTRvccxxx
30:13RWLRO3FFFFhMEM entry1 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1LADDR[45:28]vccxxx
12:11RWLRO0MEM entry1 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME1ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx124[10:0]vccxxx
Offset Address: 12B-128h (D0F2)
MEM_ENT2Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry2 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry2 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry2 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry2 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry2 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry2 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry2 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry2 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST0[3:0]vccxxx
Offset Address:12F-12Ch (D0F2)
MEM_ENT2Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry2 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry2 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry2 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry2 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry2 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry2 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry2 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry2 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2TARGET _LIST8[3:0]vccxxx
Offset Address:133-130h (D0F2)
MEM_ENT2Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry2 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2ATTRvccxxx
30:13RWLRO3FFFFhMEM entry2 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2LADDR[45:28]vccxxx
12:11RWLRO0MEM entry2 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME2ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx130[10:0]vccxxx
Offset Address: 137-134h (D0F2)
MEM_ENT3Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry3 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry3 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry3 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry3 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry3 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry3 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry3 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry3 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST0[3:0]vccxxx
Offset Address: 13B-138h (D0F2)
MEM_ENT3Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry3 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry3 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry3 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry3 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry3 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry3 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry3 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry3 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3TARGET _LIST8[3:0]vccxxx
Offset Address: 13F-13Ch (D0F2)
MEM_ENT3Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry3 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3ATTRvccxxx
30:13RWLRO3FFFFhMEM entry3 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3LADDR[45:28]vccxxx
12:11RWLRO0MEM entry3 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME3ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx13C[11:0]vccxxx
Offset Address: 143-140h (D0F2)
MEM_ENT4Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry4 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry4 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry4 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry4 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry4 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry4 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry4 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry4 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST0[3:0]vccxxx
Offset Address: 147-144h (D0F2)
MEM_ENT4Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry4 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry4 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry4 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry4 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry4 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry4 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry4 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry4 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4TARGET _LIST8[3:0]vccxxx
Offset Address: 14B-148h (D0F2)
MEM_ENT4Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry4 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4ATTRvccxxx
30:13RWLRO3FFFFhMEM entry4 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4LADDR[45:28]vccxxx
12:11RWLRO0MEM entry4 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME4ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx148[10:0]vccxxx
Offset Address: 14F-14Ch (D0F2)
MEM_ENT5Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry5 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry5 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry5 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry5 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry5 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry5 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry5 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry5 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST0[3:0]vccxxx
Offset Address:153-150h (D0F2)
MEM_ENT5Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry5 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry5 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry5 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry5 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry5 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry5 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry5 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry5 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5TARGET _LIST8[3:0]vccxxx
Offset Address:157-154h (D0F2)
MEM_ENT5Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry5 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5ATTRvccxxx
30:13RWLRO3FFFFhMEM entry5 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5LADDR[45:28]vccxxx
12:11RWLRO0MEM entry5 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME5ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx154[10:0]vccxxx
Offset Address: 15B-158h (D0F2)
MEM_ENT6Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry6 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry6 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry6 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry6 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry6 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry6 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry6 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry6 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST0[3:0]vccxxx
Offset Address: 15F-15Ch (D0F2)
MEM_ENT6Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry6 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry6 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry6 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry6 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry6 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry6 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry6 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry6 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6TARGET _LIST8[3:0]vccxxx
Offset Address: 163-160h (D0F2)
MEM_ENT6Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry6 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6ATTRvccxxx
30:13RWLRO3FFFFhMEM entry6 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6LADDR[45:28]vccxxx
12:11RWLRO0MEM entry6 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME6ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx160[11:0]vccxxx
Offset Address: 167-164h (D0F2)
MEM_ENT7Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry7 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry7 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry7 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry7 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry7 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry7 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry7 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry7 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST0[3:0]vccxxx
Offset Address: 16B-168h (D0F2)
MEM_ENT7Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry7 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry7 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry7 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry7 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry7 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry7 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry7 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry7 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7TARGET _LIST8[3:0]vccxxx
Offset Address: 16F-16Ch (D0F2)
MEM_ENT7Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry7 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7ATTRvccxxx
30:13RWLRO3FFFFhMEM entry7 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7LADDR[45:28]vccxxx
12:11RWLRO0MEM entry7 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME7ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx16C[10:0]vccxxx
Offset Address: 173-170h (D0F2)
MEM_ENT8Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry8 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry8 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry8 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry8 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry8 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry8 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry8 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry8 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST0[3:0]vccxxx
Offset Address:177-174h (D0F2)
MEM_ENT8Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry8 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry8 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry8 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry8 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry8 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry8 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry8 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry8 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8TARGET _LIST8[3:0]vccxxx
Offset Address:17B-178h (D0F2)
MEM_ENT8Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry8 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8ATTRvccxxx
30:13RWLRO3FFFFhMEM entry8 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8LADDR[45:28]vccxxx
12:11RWLRO0MEM entry8 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME8ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx178[10:0]vccxxx
Offset Address: 17F-17Ch (D0F2)
MEM_ENT9Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry9 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry9 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry9 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry9 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry9 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry9 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry9 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry9 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST0[3:0]vccxxx
Offset Address: 183-180h (D0F2)
MEM_ENT9Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry9 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry9 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry9 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry9 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry9 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry9 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry9 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry9 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9TARGET _LIST8[3:0]vccxxx
Offset Address: 187-184h (D0F2)
MEM_ENT9Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry9 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9ATTRvccxxx
30:13RWLRO3FFFFhMEM entry9 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9LADDR[45:28]vccxxx
12:11RWLRO0MEM entry9 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME9ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx184[11:0]vccxxx
Offset Address: 18B-188h (D0F2)
MEM_ENT10Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry10 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry10 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry10 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry10 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry10 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry10 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry10 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry10 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST0[3:0]vccxxx
Offset Address: 18F-18Ch (D0F2)
MEM_ENT10Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry10 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry10 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry10 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry10 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry10 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry10 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry10 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry10 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10TARGET _LIST8[3:0]vccxxx
Offset Address: 193-190h (D0F2)
MEM_ENT10Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry10 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10ATTRvccxxx
30:13RWLRO3FFFFhMEM entry10 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10LADDR[45:28]vccxxx
12:11RWLRO0MEM entry10 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME10ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx190[10:0]vccxxx
Offset Address: 197-194h (D0F2)
MEM_ENT11Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry11 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry11 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry11 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry11 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry11 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry11 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry11 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry11 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST0[3:0]vccxxx
Offset Address:19B-198h (D0F2)
MEM_ENT11Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry11 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry11 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry11 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry11 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry11 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry11 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry11 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry11 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11TARGET _LIST8[3:0]vccxxx
Offset Address:19F-19Ch (D0F2)
MEM_ENT11Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry11 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11ATTRvccxxx
30:13RWLRO3FFFFhMEM entry11 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11LADDR[45:28]vccxxx
12:11RWLRO0MEM entry11 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME11ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx19C[10:0]vccxxx
Offset Address: 1A3-1A0h (D0F2)
MEM_ENT12Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry12 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry12 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry12 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry12 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry12 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry12 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry12 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry12 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST0[3:0]vccxxx
Offset Address: 1A7-1A4h (D0F2)
MEM_ENT12Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry12 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry12 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry12 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry12 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry12 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry12 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry12 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry12 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12TARGET _LIST8[3:0]vccxxx
Offset Address: 1AB-1A8h (D0F2)
MEM_ENT12Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry12 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12ATTRvccxxx
30:13RWLRO3FFFFhMEM entry12 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12LADDR[45:28]vccxxx
12:11RWLRO0MEM entry12 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME12ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1A8[11:0]vccxxx
Offset Address: 1AF-1ACh (D0F2)
MEM_ENT13Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry13 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry13 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry13 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry13 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry13 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry13 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry13 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry13 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST0[3:0]vccxxx
Offset Address: 1B3-1B0h (D0F2)
MEM_ENT13Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry13 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry13 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry13 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry13 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry13 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry13 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry13 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry13 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13TARGET_LIST8[3:0]vccxxx
Offset Address: 1B7-1B4h (D0F2)
MEM_ENT13Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry13 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13ATTRvccxxx
30:13RWLRO3FFFFhMEM entry13 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13LADDR[45:28]vccxxx
12:11RWLRO0MEM entry13 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME13ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1B4[10:0]vccxxx
Offset Address: 1BB-1B8h (D0F2)
MEM_ENT14Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry14 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry14 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry14 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry14 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry14 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry14 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry14 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry14 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST0[3:0]vccxxx
Offset Address:1BF-1BCh (D0F2)
MEM_ENT14Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry14 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry14 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry14 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry14 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry14 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry14 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry14 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry14 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14TARGET _LIST8[3:0]vccxxx
Offset Address:1C3-1C0h (D0F2)
MEM_ENT14Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry14 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14ATTRvccxxx
30:13RWLRO3FFFFhMEM entry14 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14LADDR[45:28]vccxxx
12:11RWLRO0MEM entry14 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME14ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1C0[10:0]vccxxx
Offset Address: 1C7-1C4h (D0F2)
MEM_ENT15Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry15 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry15 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry15 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry15 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry15 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry15 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry15 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry15 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST0[3:0]vccxxx
Offset Address: 1CB-1C8h (D0F2)
MEM_ENT15Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry15 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry15 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry15 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry15 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry15 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry15 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry15 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry15 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15TARGET _LIST8[3:0]vccxxx
Offset Address: 1CF-1CCh (D0F2)
MEM_ENT15Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry15 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15ATTRvccxxx
30:13RWLRO3FFFFhMEM entry15 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15LADDR[45:28]vccxxx
12:11RWLRO0MEM entry15 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME15ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1CC[11:0]vccxxx
Offset Address: 1D3-1D0h (D0F2)
MEM_ENT16Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry16 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry16 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry16 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry16 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry16 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry16 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry16 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry16 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST0[3:0]vccxxx
Offset Address: 1D7-1D4h (D0F2)
MEM_ENT16Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry16 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry16 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry16 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry16 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry16 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry16 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry16 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry16 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16TARGET _LIST8[3:0]vccxxx
Offset Address: 1DB-1D8h (D0F2)
MEM_ENT16Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry16 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16ATTRvccxxx
30:13RWLRO3FFFFhMEM entry16 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16LADDR[45:28]vccxxx
12:11RWLRO0MEM entry16 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME16ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1D8[10:0]vccxxx
Offset Address: 1DF-1DCh (D0F2)
MEM_ENT17Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry17 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry17 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry17 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry17 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry17 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry17 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry17 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry17 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST0[3:0]vccxxx
Offset Address:1E3-1E0h (D0F2)
MEM_ENT17Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry17 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry17 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry17 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry17 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry17 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry17 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry17 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry17 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17TARGET _LIST8[3:0]vccxxx
Offset Address:1E7-1E4h (D0F2)
MEM_ENT17Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry17 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17ATTRvccxxx
30:13RWLRO3FFFFhMEM entry17 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17LADDR[45:28]vccxxx
12:11RWLRO0MEM entry17 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME17ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1E4[10:0]vccxxx
Offset Address: 1EB-1E8h (D0F2)
MEM_ENT18Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry18 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry18 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry18 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry18 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry18 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry18 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry18 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry18 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST0[3:0]vccxxx
Offset Address: 1EF-1ECh (D0F2)
MEM_ENT18Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry18 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry18 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry18 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry18 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry18 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry18 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry18 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry18 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18TARGET _LIST8[3:0]vccxxx
Offset Address: 1F3-1F0h (D0F2)
MEM_ENT18Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry18 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18ATTRvccxxx
30:13RWLRO3FFFFhMEM entry18 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18LADDR[45:28]vccxxx
12:11RWLRO0MEM entry18 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME18ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1F0[11:0]vccxxx
Offset Address: 1F7-1F4h (D0F2)
MEM_ENT19Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry19 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry19 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry19 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry19 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry19 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry19 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry19 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry19 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST0[3:0]vccxxx
Offset Address: 1FB-1F8h (D0F2)
MEM_ENT19Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry19 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry19 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry19 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry19 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry19 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry19 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry19 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry19 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19TARGET _LIST8[3:0]vccxxx
Offset Address: 1FF-1FCh (D0F2)
MEM_ENT19Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry19 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19ATTRvccxxx
30:13RWLRO3FFFFhMEM entry19 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19LADDR[45:28]vccxxx
12:11RWLRO0MEM entry19 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME19ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx1FC[10:0]vccxxx
Offset Address: 203-200h (D0F2)
MEM_ENT20Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry20 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry20 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry20 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry20 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry20 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry20 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry20 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry20 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST0[3:0]vccxxx
Offset Address:207-204h (D0F2)
MEM_ENT20Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry20 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry20 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry20 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry20 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry20 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry20 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry20 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry20 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20TARGET _LIST8[3:0]vccxxx
Offset Address:20B-208h (D0F2)
MEM_ENT20Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry20 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20ATTRvccxxx
30:13RWLRO3FFFFhMEM entry20 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20LADDR[45:28]vccxxx
12:11RWLRO0MEM entry20 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME20ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx208[10:0]vccxxx
Offset Address: 20F-20Ch (D0F2)
MEM_ENT21Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry21 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry21 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry21 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry21 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry21 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry21 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry21 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry21 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST0[3:0]vccxxx
Offset Address: 213-210h (D0F2)
MEM_ENT21Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry21 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry21 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry21 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry21 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry21 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry21 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry21 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry21 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21TARGET _LIST8[3:0]vccxxx
Offset Address: 217-214h (D0F2)
MEM_ENT21Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry21 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21ATTRvccxxx
30:13RWLRO3FFFFhMEM entry21 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21LADDR[45:28]vccxxx
12:11RWLRO0MEM entry21 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME21ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx214[11:0]vccxxx
Offset Address: 21B-218h (D0F2)
MEM_ENT22Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry22 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry22 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry22 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry22 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry22 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry22 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry22 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry22 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST0[3:0]vccxxx
Offset Address: 21F-21Ch (D0F2)
MEM_ENT22Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry22 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry22 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry22 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry22 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry22 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry22 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry22 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry22 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22TARGET _LIST8[3:0]vccxxx
Offset Address: 223-220h (D0F2)
MEM_ENT22Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry22 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22ATTRvccxxx
30:13RWLRO3FFFFhMEM entry22 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22LADDR[45:28]vccxxx
12:11RWLRO0MEM entry22 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME22ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx220[10:0]vccxxx
Offset Address: 227-224h (D0F2)
MEM_ENT23Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry23 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry23 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry23 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry23 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry23 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry23 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry23 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry23 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST0[3:0]vccxxx
Offset Address:22B-228h (D0F2)
MEM_ENT23Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry23 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry23 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry23 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry23 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry23 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry23 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry23 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry23 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23TARGET _LIST8[3:0]vccxxx
Offset Address:22F-22Ch (D0F2)
MEM_ENT23Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry23 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23ATTRvccxxx
30:13RWLRO3FFFFhMEM entry23 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23LADDR[45:28]vccxxx
12:11RWLRO0MEM entry23 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME23ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx22C[10:0]vccxxx
Offset Address: 233-230h (D0F2)
MEM_ENT24Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry24 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry24 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry24 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry24 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry24 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry24 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry24 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry24 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST0[3:0]vccxxx
Offset Address: 237-234h (D0F2)
MEM_ENT24Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry24 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry24 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry24 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry24 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry24 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry24 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry24 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry24 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24TARGET _LIST8[3:0]vccxxx
Offset Address: 23B-238h (D0F2)
MEM_ENT24Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry24 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24ATTRvccxxx
30:13RWLRO3FFFFhMEM entry24 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24LADDR[45:28]vccxxx
12:11RWLRO0MEM entry24 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME24ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx238[11:0]vccxxx
Offset Address: 23F-23Ch (D0F2)
MEM_ENT25Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry1 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry1 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry1 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry1 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry1 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry1 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry1 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry1 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST0[3:0]vccxxx
Offset Address: 243-240h (D0F2)
MEM_ENT25Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry1 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry1 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry1 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry1 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry1 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry1 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry1 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry1 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25TARGET _LIST8[3:0]vccxxx
Offset Address: 247-244h (D0F2)
MEM_ENT25Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry1 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25ATTRvccxxx
30:13RWLRO3FFFFhMEM entry1 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25LADDR[45:28]vccxxx
12:11RWLRO0MEM entry1 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME25ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx244[10:0]vccxxx
Offset Address: 24B-248h (D0F2)
MEM_ENT26Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry2 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry2 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry2 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry2 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry2 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry2 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry2 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry2 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST0[3:0]vccxxx
Offset Address:24F-24Ch (D0F2)
MEM_ENT26Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry2 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry2 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry2 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry2 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry2 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry2 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry2 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry2 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26TARGET _LIST8[3:0]vccxxx
Offset Address:253-250h (D0F2)
MEM_ENT26Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry2 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26ATTRvccxxx
30:13RWLRO3FFFFhMEM entry2 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26LADDR[45:28]vccxxx
12:11RWLRO0MEM entry2 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME26ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx250[10:0]vccxxx
Offset Address: 257-254h (D0F2)
MEM_ENT27Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry27 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry27 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry27 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry27 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry27 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry27 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry27 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry27 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST0[3:0]vccxxx
Offset Address: 25B-258h (D0F2)
MEM_ENT27Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry27 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry27 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry27 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry27 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry27 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry27 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry27 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry27 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27TARGET _LIST8[3:0]vccxxx
Offset Address: 25F-25Ch (D0F2)
MEM_ENT27Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry27 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27ATTRvccxxx
30:13RWLRO3FFFFhMEM entry27 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27LADDR[45:28]vccxxx
12:11RWLRO0MEM entry27 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME27ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx25C[11:0]vccxxx
Offset Address: 263-260h (D0F2)
MEM_ENT28Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry28 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry28 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry28 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry28 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry28 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry28 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry28 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry28 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST0[3:0]vccxxx
Offset Address: 267-264h (D0F2)
MEM_ENT28Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry28 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry28 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry28 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry28 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry28 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry28 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry28 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry28 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28TARGET _LIST8[3:0]vccxxx
Offset Address: 26B-268h (D0F2)
MEM_ENT28Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry28 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28ATTRvccxxx
30:13RWLRO3FFFFhMEM entry28 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28LADDR[45:28]vccxxx
12:11RWLRO0MEM entry28 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME28ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx268[10:0]vccxxx
Offset Address: 26F-26Ch (D0F2)
MEM_ENT29Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry29 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry29 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry29 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry29 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry29 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry29 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry29 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry29 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST0[3:0]vccxxx
Offset Address:273-270h (D0F2)
MEM_ENT29Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry29 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry29 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry29 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry29 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry29 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry29 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry29 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry29 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29TARGET _LIST8[3:0]vccxxx
Offset Address:277-274h (D0F2)
MEM_ENT29Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry29 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29ATTRvccxxx
30:13RWLRO3FFFFhMEM entry29 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29LADDR[45:28]vccxxx
12:11RWLRO0MEM entry29 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME29ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx274[10:0]vccxxx
Offset Address: 27B-278h (D0F2)
MEM_ENT30Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry30 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry30 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry30 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry30 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry30 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry30 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry30 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry30 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST0[3:0]vccxxx
Offset Address: 27F-27Ch (D0F2)
MEM_ENT30Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry30 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry30 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry30 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry30 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry30 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry30 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry30 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry30 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30TARGET _LIST8[3:0]vccxxx
Offset Address: 283-280h (D0F2)
MEM_ENT30Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry30 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30ATTRvccxxx
30:13RWLRO3FFFFhMEM entry30 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30LADDR[45:28]vccxxx
12:11RWLRO0MEM entry30 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME30ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx280[11:0]vccxxx
Offset Address: 287-284h (D0F2)
MEM_ENT31Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry31 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry31 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry31 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry31 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry31 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry31 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry31 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry31 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST0[3:0]vccxxx
Offset Address: 28B-288h (D0F2)
MEM_ENT31Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry31 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry31 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry31 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry31 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry31 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry31 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry31 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry31 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31TARGET _LIST8[3:0]vccxxx
Offset Address: 28F-28Ch (D0F2)
MEM_ENT31Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry31 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31ATTRvccxxx
30:13RWLRO3FFFFhMEM entry31 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31LADDR[45:28]vccxxx
12:11RWLRO0MEM entry31 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME31ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx28C[10:0]vccxxx
Offset Address: 293-290h (D0F2)
MEM_ENT32Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry32 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry32 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry32 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry32 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry32 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry32 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry32 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry32 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST0[3:0]vccxxx
Offset Address:297-294h (D0F2)
MEM_ENT32Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry32 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry32 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry32 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry32 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry32 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry32 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry32 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry32 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32TARGET _LIST8[3:0]vccxxx
Offset Address:29B-298h (D0F2)
MEM_ENT32Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry32 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32ATTRvccxxx
30:13RWLRO3FFFFhMEM entry32 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32LADDR[45:28]vccxxx
12:11RWLRO0MEM entry32 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME32ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx298[10:0]vccxxx
Offset Address: 29F-29Ch (D0F2)
MEM_ENT33Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry33 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry33 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry33 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry33 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry33 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry33 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry33 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry33 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST0[3:0]vccxxx
Offset Address: 2A3-2A0h (D0F2)
MEM_ENT33Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry33 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry33 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry33 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry33 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry33 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry33 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry33 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry33 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33TARGET _LIST8[3:0]vccxxx
Offset Address: 2A7-2A4h (D0F2)
MEM_ENT33Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry33 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33ATTRvccxxx
30:13RWLRO3FFFFhMEM entry33 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33LADDR[45:28]vccxxx
12:11RWLRO0MEM entry33 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME33ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx2A4[11:0]vccxxx
Offset Address: 2AB-2A8h (D0F2)
MEM_ENT34Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry34 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry34 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry34 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry34 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry34 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry34 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry34 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry34 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST0[3:0]vccxxx
Offset Address: 2AF-2ACh (D0F2)
MEM_ENT34Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry34 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry34 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry34 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry34 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry34 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry34 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry34 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry34 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34TARGET _LIST8[3:0]vccxxx
Offset Address: 2B3-2B0h (D0F2)
MEM_ENT34Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry34 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34ATTRvccxxx
30:13RWLRO3FFFFhMEM entry34 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34LADDR[45:28]vccxxx
12:11RWLRO0MEM entry34 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME34ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx2B0[10:0]vccxxx
Offset Address: 2B7-2B4h (D0F2)
MEM_ENT35Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry35 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry35 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry35 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry35 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry35 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry35 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry35 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry35 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST0[3:0]vccxxx
Offset Address:2BB-2B8h (D0F2)
MEM_ENT35Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry35 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry35 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry35 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry35 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry35 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry35 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry35 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry35 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35TARGET _LIST8[3:0]vccxxx
Offset Address:2BF-2BCh (D0F2)
MEM_ENT35Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry35 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35ATTRvccxxx
30:13RWLRO3FFFFhMEM entry35 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35LADDR[45:28]vccxxx
12:11RWLRO0MEM entry35 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME35ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx2BC[10:0]vccxxx
Offset Address: 2C3-2C0h (D0F2)
MEM_ENT36Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry36 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry36 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry36 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry36 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry36 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry36 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry36 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry36 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST0[3:0]vccxxx
Offset Address: 2C7-2C4h (D0F2)
MEM_ENT36Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry36 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry36 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry36 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry36 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry36 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry36 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry36 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry36 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36TARGET _LIST8[3:0]vccxxx
Offset Address: 2CB-2C8h (D0F2)
MEM_ENT36Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry36 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36ATTRvccxxx
30:13RWLRO3FFFFhMEM entry36 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36LADDR[45:28]vccxxx
12:11RWLRO0MEM entry36 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME36ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx2C8[11:0]vccxxx
Offset Address: 2CF-2CCh (D0F2)
MEM_ENT37Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry37 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry37 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry37 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry37 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry37 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry37 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry37 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry37 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST0[3:0]vccxxx
Offset Address: 2D3-2D0h (D0F2)
MEM_ENT37Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry37 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry37 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry37 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry37 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry37 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry37 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry37 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry37 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37TARGET_LIST8[3:0]vccxxx
Offset Address: 2D7-2D4h (D0F2)
MEM_ENT37Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry37 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37ATTRvccxxx
30:13RWLRO3FFFFhMEM entry37 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37LADDR[45:28]vccxxx
12:11RWLRO0MEM entry37 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME37ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx2D4[10:0]vccxxx
Offset Address: 2DB-2D8h (D0F2)
MEM_ENT38Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry38 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry38 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry38 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry38 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry38 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry38 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry38 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry38 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST0[3:0]vccxxx
Offset Address:2DF-2DCh (D0F2)
MEM_ENT38Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry38 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry38 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry38 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry38 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry38 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry38 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry38 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry38 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38TARGET _LIST8[3:0]vccxxx
Offset Address:2E3-2E0h (D0F2)
MEM_ENT38Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry38 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38ATTRvccxxx
30:13RWLRO3FFFFhMEM entry38 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38LADDR[45:28]vccxxx
12:11RWLRO0MEM entry38 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME38ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx2E0[10:0]vccxxx
Offset Address: 2E7-2E4h (D0F2)
MEM_ENT39Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry39 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry39 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry39 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry39 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry39 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry39 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry39 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry39 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST0[3:0]vccxxx
Offset Address: 2EB-2E8h (D0F2)
MEM_ENT39Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry39 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry39 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry39 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry39 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry39 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry39 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry39 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry39 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39TARGET _LIST8[3:0]vccxxx
Offset Address: 2EF-2ECh (D0F2)
MEM_ENT39Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry39 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39ATTRvccxxx
30:13RWLRO3FFFFhMEM entry39 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39LADDR[45:28]vccxxx
12:11RWLRO0MEM entry39 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME39ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx2EC[11:0]vccxxx
Offset Address: 2F3-2F0h (D0F2)
MEM_ENT40Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry40 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry40 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry40 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry40 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry40 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry40 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry40 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry40 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST0[3:0]vccxxx
Offset Address: 2F7-2F4h (D0F2)
MEM_ENT40Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry40 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry40 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry40 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry40 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry40 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry40 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry40 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry40 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40TARGET _LIST8[3:0]vccxxx
Offset Address: 2FB-2F8h (D0F2)
MEM_ENT40Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry40 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40ATTRvccxxx
30:13RWLRO3FFFFhMEM entry40 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40LADDR[45:28]vccxxx
12:11RWLRO0MEM entry40 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME40ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx12F8[10:0]vccxxx
Offset Address: 2FF-2FCh (D0F2)
MEM_ENT41Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry41 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry41 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry41 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry41 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry41 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry41 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry41 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry41 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST0[3:0]vccxxx
Offset Address:303-300h (D0F2)
MEM_ENT41Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry41 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry41 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry41 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry41 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry41 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry41 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry41 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry41 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41TARGET _LIST8[3:0]vccxxx
Offset Address:307-304h (D0F2)
MEM_ENT41Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry41 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41ATTRvccxxx
30:13RWLRO3FFFFhMEM entry41 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41LADDR[45:28]vccxxx
12:11RWLRO0MEM entry41 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME41ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx304[10:0]vccxxx
Offset Address: 30B-308h (D0F2)
MEM_ENT42Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry42 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry42 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry42 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry42 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry42 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry42 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry42 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry42 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST0[3:0]vccxxx
Offset Address: 30F-30Ch (D0F2)
MEM_ENT42Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry42 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry42 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry42 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry42 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry42 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry42 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry42 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry42 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42TARGET _LIST8[3:0]vccxxx
Offset Address: 313-310h (D0F2)
MEM_ENT42Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry42 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42ATTRvccxxx
30:13RWLRO3FFFFhMEM entry42 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42LADDR[45:28]vccxxx
12:11RWLRO0MEM entry42 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME42ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx310[11:0]vccxxx
Offset Address: 317-314h (D0F2)
MEM_ENT43Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry43 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry43 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry43 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry43 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry43 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry43 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry43 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry43 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST0[3:0]vccxxx
Offset Address: 31B-318h (D0F2)
MEM_ENT43Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry43 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry43 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry43 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry43 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry43 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry43 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry43 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry43 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43TARGET _LIST8[3:0]vccxxx
Offset Address: 31F-31Ch (D0F2)
MEM_ENT43Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry43 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43ATTRvccxxx
30:13RWLRO3FFFFhMEM entry43 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43LADDR[45:28]vccxxx
12:11RWLRO0MEM entry43 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME43ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx31C[10:0]vccxxx
Offset Address: 323-320h (D0F2)
MEM_ENT44Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry44 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry44 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry44 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry44 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry44 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry44 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry44 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry44 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST0[3:0]vccxxx
Offset Address:327-324h (D0F2)
MEM_ENT44Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry44 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry44 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry44 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry44 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry44 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry44 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry44 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry44 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44TARGET _LIST8[3:0]vccxxx
Offset Address:32B-328h (D0F2)
MEM_ENT44Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry44 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44ATTRvccxxx
30:13RWLRO3FFFFhMEM entry44 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44LADDR[45:28]vccxxx
12:11RWLRO0MEM entry44 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME44ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx328[10:0]vccxxx
Offset Address: 32F-32Ch (D0F2)
MEM_ENT45Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry45 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry45 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry45 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry45 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry45 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry45 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry45 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry45 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST0[3:0]vccxxx
Offset Address: 333-330h (D0F2)
MEM_ENT45Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry45 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry45 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry45 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry45 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry45 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry45 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry45 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry45 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45TARGET _LIST8[3:0]vccxxx
Offset Address: 337-334h (D0F2)
MEM_ENT45Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry45 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45ATTRvccxxx
30:13RWLRO3FFFFhMEM entry45 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45LADDR[45:28]vccxxx
12:11RWLRO0MEM entry45 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME45ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx334[11:0]vccxxx
Offset Address: 33B-338h (D0F2)
MEM_ENT46Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry46 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry46 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry46 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry46 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry46 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET _LIST3[3:0]vccxxx
11:8RWLRO0MEM entry46 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry46 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry46 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST0[3:0]vccxxx
Offset Address: 33F-33ch (D0F2)
MEM_ENT46Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry46 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry46 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry46 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry46 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry46 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry46 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry46 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry46 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46TARGET _LIST8[3:0]vccxxx
Offset Address: 343-340h (D0F2)
MEM_ENT46Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry46 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46ATTRvccxxx
30:13RWLRO3FFFFhMEM entry46 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46LADDR[45:28]vccxxx
12:11RWLRO0MEM entry46 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME46ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx340[10:0]vccxxx
Offset Address: 347-344h (D0F2)
MEM_ENT47Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry47 TARGET LIST7 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST7[3:0]vccxxx
27:24RWLRO0MEM entry47 TARGET LIST6 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST6[3:0]vccxxx
23:20RWLRO0MEM entry47 TARGET LIST5 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST5[3:0]vccxxx
19:16RWLRO0MEM entry47 TARGET LIST4 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST4[3:0]vccxxx
15:12RWLRO0MEM entry47 TARGET LIST3 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST3[3:0]vccxxx
11:8RWLRO0MEM entry47 TARGET LIST2 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST2[3:0]vccxxx
7:4RWLRO0MEM entry47 TARGET LIST1 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST1[3:0]vccxxx
3:0RWLRO0MEM entry47 TARGET LIST0 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST0[3:0]vccxxx
Offset Address:34B-348h (D0F2)
MEM_ENT47Default Value: 0000 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:28RWLRO0MEM entry47 TARGET LIST15 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST15[3:0]vccxxx
27:24RWLRO0MEM entry47 TARGET LIST14 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST14[3:0]vccxxx
23:20RWLRO0MEM entry47 TARGET LIST13 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST13[3:0]vccxxx
19:16RWLRO0MEM entry47 TARGET LIST12 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST12[3:0]vccxxx
15:12RWLRO0MEM entry47 TARGET LIST11 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST11[3:0]vccxxx
11:8RWLRO0MEM entry47 TARGET LIST10 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST10[3:0]vccxxx
7:4RWLRO0MEM entry47 TARGET LIST9 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET_LIST9[3:0]vccxxx
3:0RWLRO0MEM entry47 TARGET LIST8 for target decode
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47TARGET _LIST8[3:0]vccxxx
Offset Address:34F-34Ch (D0F2)
MEM_ENT47Default Value:
7FFF E000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31RWLRO0MEM entry47 attr
Indicate the region's memory attribute.
1'b0: Memory;
1'b1: MMIO;
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47ATTRvccxxx
30:13RWLRO3FFFFhMEM entry47 limit addr
Memory decoder entry address limit, unit of 256M bytes.
0: means address limit = 256M -1 bytes
1: means address limit =  (1+1)x256M – 1 bytes
N: means  address limit = (N+1)x256M – 1 bytes
For an address X, When Base address <= X <= limit address then hit this entry
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47LADDR[45:28]vccxxx
12:11RWLRO0MEM entry47 interleave addr bit sel
2’b00: A[9:6] 2’b01:A[10:7] 2’b10:A[11:8]
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
((For Internal Reference: The register is for SVAD.))
((For Internal Reference: @((#USER=HIF)) ))
RSVAD_ME47ADDR_SEL_11_9vccxxx
10:0RONA0Reserved Rx34C[10:0]vccxxx

RTopA and LowTopA (350-3FFh)

Offset Address: 353-350h (D0F2)
Highest SVAD limit target to memory (DRAM limit address over 4G)Default Value:
FFFF FFC0h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
31:6RWLRO3FFFFFFhTOP of System memory address over 4G
these bits defined the TOP address space over 4G that the system can use as the system memory.
The address X of “4G<=X<RTOPA” is the DRAM address.
BIOS should set RTOPA = 1000h if no system memory above 4G address
This register is used for traffic controller to decode target of the upstream cycle to memory or MMIO(PCI) for P2P
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
RTOPA[45:20]vccxxx
5:0RONA0Reserved Rx318[3:0]vccxxx
Offset Address: 355-354h (D0F2)
Below 4G highest memory limit(DRAM limit address below 4G)Default Value: FF00h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:4RWLROFF0hTOP of System memory address below 4G
these bits defined the TOP address space below 4G that the system can use as the system memory.
Note: BIOS MUST set Below 4G MMIO Base address  = RLOWTOPA = min value of {MMIOB2G, MMIO2T4G}
The address X of “X < RLOWTOPA”is the DRAM address.
HW use the RLOWTOPA to decode the P2C cycle target to DRAM or MMIO.
((For Internal Reference: This bit is RW when D0F2 Rx90 [30] is set to 0.
@((#control_lock = lock_port RSVAD_LOCK)) ))
RLOWTOPA[31:20]vccxxx
3:0RONA0Reserved Rx354[3:0]vccxxx
Offset Address: 356-3FFh (D0F2) – Reserved
Offset Address: 320-3FFh (D0F0) – Reserved

TPR Control (400-40Fh)

Offset Address: 400-40Bh (D0F0(D0F2) – Reserved
Offset Address: 40D-40Ch (D0F2)
ReservedDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:0RONA0ReservedRxcc[15:0]vccxxx
Offset Address: 40F-40Eh (D0F2)
TPR ControlDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:5RONA0ReservedRxce[15:5]vccxxx
4RWRO0APIC Round-Robin Mode Select
When enable the round-robin mechanism (RAPICROEN=1), There are two modes to control round-robin method
0: Round-Robin base on each core’s TPR value and select target core
1: Treat all cores as same TPR value and round-robin to select target core, in this case, ignore all TPR value configured from TPR cycle.  
((For Internal Reference: @((#TOGGLE=1))  ))
RAPICROMODESELvcc0xx
3RWNA0Reserved
((For Internal Reference:
APIC Cluster Model Select
There are two ways to decide HIF is in APIC Cluster Model (Note 1) or not.  One is auto mode, in this way, HIF will decide whether or not it is in Cluster model according to APIC_CM_EN (Note 2) which is set by CPU’s TPR cycle; the other way is SW control mode, in this way, HIF will decide whether or not it is in Cluster mode according to Register RAPICCMSWEN.

0: Auto mode

1: Software control mode

Notes:
  1. In logical destination mode, CPU support flat model and Cluster model. Controlled by Destination Format Register in local apic. in Flat model, CPU bit match with Destination field of MSI with Logical APIC ID field in Logical Destination Register of local APIC. The Flat model  support up to 8 cores. In Cluster model, the bit [7:4] in Logical APIC ID field is Cluster ID and bit [3:0]  in Logical APIC ID field bit match for target cpu cores in this cluster. It support Cluster ID from 0h to Eh, total 15 Cluster ID and support 4 cores in each Cluster ID. Total support 15x4 = 60 cores in Cluster model.
  2. When CPU in Cluster model, it will issue TPR cycle with APIC_CM_EN=1.
  3. When Cluster ID = Fh, Means broadcast Cluster ID, all CPU treat it as Cluster ID hit.
))
RAPICCMSvcc0xx
2RWNA0Reserved
((For Internal Reference:
APIC Round-Robin Mechanism Enable
When enable the round-robin mechanism, if there are two cores which have the same priority, HIF will not always choose the core which core number is little, but choose the two cores in turn.
0: Disable1: Enable
))
((For Internal Reference: @((#TOGGLE=1)) ))
RAPICROENvcc0xx
1RWNA0Reserved
((For Internal Reference:
APIC Cluster Model Software Enable
0: Disable APIC Cluster Model
1: Enable APIC Cluster Model
))
RAPICCMSWENvcc0xx
0RWNA0Reserved
((For Internal Reference:
Redirect Lowest Priority MSI Requests to CPU Core0
For supporting the FSB interrupt delivery, this chip is able to redirect the coming in MSI cycle to the CPU with least task priority. This register is used to redirect the Lowest Priority MSI Request cycle to the CPU core0 (CPU0 is treated as the lowest priority processor).
0: Disable. The Lowest Priority MSI Request will be redirected to lowest priority CPU core according to TPR Table record.
1: Enable. The Lowest Priority MSI Request will be always redirected to CPU core0.
))
RAPIC0vcc00x


Interrupt Message Address Format

BitDescription
31:20always be 0xFEE
19:12Destination ID
11:4will always be 0
3Redirection Hint
2Destination Mode
1:0always be 00

Interrupt Message Data Format

BitDescription
31:16always be 0000h
15Trigger Mode
14Delivery Status
13:12always be 00
11always be 0
10:8Delivery mode
7:0Vector

DMA Protection Control (410-41Fh)

Offset Address: 411-410h (D0F2)
DMA Protection ControlDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:12RWRO0ReservedRx410[15:12]vcc0xx
11:4RWLRO0This is the Size of DPR Region in MB
It can be locked by Rx410[0]
((For Internal Reference: This bit is RW when D0F2 DPR_LOCK is set to 0.
@((#control_lock = lock_port DPR_LOCK)) ))
DPR_SIZE[7:0]vcc*xx
3RWRO0ReservedRx410[3]vcc0xx
2RWLRO0DPR Enable
0: Disable DPR1: Enable DPR
((For Internal Reference: This bit is RW when D0F2 DPR_LOCK is set to 0.
@((#control_lock = lock_port DPR_LOCK)) ))
DPR_ENvcc*xx
1RONA0ReservedDPR_STSvcc0xx
0RWLRO0Lock Bit to Lock DMA Protection Control
0: No effect
1: Bits 11:0 will be locked down in this register.
((For Internal Reference: This bit is RW when D0F2 DPR_LOCK is set to 0.
@((#control_lock = lock_port DPR_LOCK)) ))
DPR_LOCKvcc0xx
Offset Address: 413-412h (D0F2)
ReservedDefault Value: 0000h
BitAttributeHW PropertyDefaultDescriptionMnemonicChipRevPwrDmSPE
15:0RONA0ReservedRx412[15:0]vcc0xx
Offset Address: 414-41Fh (D0F2) – Reserved

([TIC Question 1. End of questions. Thanks!])